Computer Architecture Lecture 3 Combinational Circuits Ralph Grishman September 2015 NYU

Time and Frequency time = 1 / frequency frequency = 1 / time units of time millisecond = second microsecond = second nanosecond = second picosecond = second units of frequency kiloHertz (kHz) = 10 3 cycles / second megaHertz (MHz) = 10 6 cycles / second gigaHertz (GHz) = 10 9 cycles / second 9/14/15Computer Architecture lecture 32

Today’s Problem A typical clock frequency for current PCs is 2 GHz. What is the corresponding clock period? (a) 200 ps (b) 500 ps (c) 2 ns (d) 5 ns 9/14/15Computer Architecture lecture 33

Solution Frequency = 2 GHz = 2 * 10 9 Hz Period = 1 / frequency = 1 / (2 * 10 9 ) sec = (1 / 2) * (1 / 10 9 ) sec = 0.5 * sec = 0.5 ns = 500 * sec = 500 ps 9/14/15Computer Architecture lecture 34

Assignment #1 various short questions about combinational circuits 9/14/15Computer Architecture lecture 35

Design tools see lecture outline 9/14/15Computer Architecture lecture 36

Propagation Delay delay of individual transistor -- how fast it can switch -- determined by physical factors (e.g., size) speed of transistor determines speed of gate 9/14/15Computer Architecture lecture 37 time voltage in out

Propagation Delay the propagation delay (speed) of a combinatorial circuit is the length of time from the moment when all input signals are stable until the moment when all outputs have stabilized 9/14/15Computer Architecture lecture 38

Propagation Delay propagation delay of a combinatorial circuit can be determined as longest path (in number of gates) from any input to any output delay=2 9/14/15Computer Architecture lecture 39

A Very Rough Estimate After transistor switches, it has to charge output wires – this may be a large part of total delay – so assuming all gate delays are the same produces a very rough estimate of circuit delays – but is good enough for understanding principles of circuit design so we will make that assumption in this course 9/14/15Computer Architecture lecture 310

Fan-in sum-of-products form suggests any combinatorial function can be computed in 3 gate delays (one delay for inverters, one for ANDs, one for OR) 9/14/15Computer Architecture lecture 311

Fan-in but gates are limited in their fan-in (number of inputs a gate has) 9/14/15Computer Architecture lecture 312

Fan-in for example, if fan-in is f, it takes log (base f) n gate delays to OR or AND together n inputs log 2 8 = 3 gate delays 9/14/15Computer Architecture lecture 313

Adders The simplest case: adding two one-bit numbers Sum = A xor B Carry = A and B 9/14/15Computer Architecture lecture 314 ABSumCarr y

n-bit Adder adding multi-bit numbers: – have to keep track of a carry out of one bit position and into the next position to the left /14/15Computer Architecture lecture 315

n-bit Adder Do this with full adders, which have 3 inputs: A, B, and C in, and 2 outputs, Sum and C out. 9/14/15Computer Architecture lecture 316 ABCinSumCout

Full Adder We will show the connections of the full adder as follows: 9/14/15Computer Architecture lecture 317 A Sum Cout B Cin

n-bit Adder Then we can draw a 3-bit adder like so: 9/14/15Computer Architecture lecture 318 Cout Cin A2 B2 A1 B1 A0 B0 Sum0 Sum2 Sum1

n-bit adder: delay ripple-carry adder: carry ripples from bit 0 to high-order bit total delay (for large n) = n * delay(Cin  Cout) 9/14/15Computer Architecture lecture 319

Signed Numbers So far we assumed the bits represent positivve numbers: 9/14/15Computer Architecture lecture

Signed Numbers We could use some of the bit patterns to represent negative numbers, like so: 9/14/15Computer Architecture lecture sign and magnitude

Signed Numbers Or like so: 9/14/15Computer Architecture lecture two’s complement

Signed Numbers Or even like so: 9/14/15Computer Architecture lecture

Why do we prefer two’s complement? 9/14/15Computer Architecture lecture 324

Why do we prefer two’s complement? Can use same logic as for unsigned addition 9/14/15Computer Architecture lecture 325

Computing two’s complement Given representation of v, how to compute representation of –v ? 9/14/15Computer Architecture lecture 326

Computing two’s complement Given representation of v, how to compute representation of –v: flip every bit in representation of v add 1 9/14/15Computer Architecture lecture 327

Computing two’s complement 9/14/15Computer Architecture lecture 328 Cout Cin Acomp0 Acomp2 Acomp1 A2 A1 A0

Subtracting B – A = B + (-A) 9/14/15Computer Architecture lecture 329 Cout Cin Acomp0 Acomp2 Acomp1 A2 A1 A0 B2 B1 B0

Can we simplify this? 9/14/15Computer Architecture lecture 330

Subtracting: B – A = B + (-A) 9/14/15Computer Architecture lecture 331 Cout Cin B2 B1 B0 (A-B)0 (A-B)2 (A-B)1 A2 A1 A0 1