May 8, USB 2.0 Signal Protocols Jon Lueker Intel Corporation

May 8, Protocol Requirements Similar to USB 1.1 w Data encoding w Packet Start/End delimiters w Connect/Disconnect detection w Suspend/Resume w Reset w Speed detection

May 8, NRZI Data Encoding w Same data encoding as LS and FS modes w 0 is encoded as a transition, 1 as no transition w Bit stuffing inserts a 0 after every 6 consecutive 1’s w Maximum number of symbols without transition is 7 (except EOP) w Bit stuffing assures sufficient transitions to keep DLL locked onto data stream

May 8, High-Speed SOP HS Idle K J K J K J K J K J K K Data Receiver squelched - Differential envelope below 100mV Differential envelope exceeds 150mV - reception enabled within four symbol times Clock recovery circuit must lock in time to detect end of SYNC End of SYNC detected, receiver begins data recovery HS SYNC Field - 32 bits

May 8, High-Speed EOP Data Bit Stuff Error SE0 Normal HS data transmission with NRZI encoding and bit stuffing First bit of the EOP field is a transition EOP field is a bit stuff violation After EOP, lines return to Idle state and receiver is squelched HS EOP Field

May 8, Disconnect Detection w Basic idea is to check for higher than normal signal voltages on the differential pair w Higher voltages will result when device terminations are removed - nominal increase is a jump from 400mV to 800mV w Check is performed during last 8 bits of EOP of uSOF frames w uSOF EOP is lengthened to 40 bits to make this mechanism reliable - duration must be longer than round-trip time of maximum length cable Device Disconnection Device Disconnection Voltage Threshold Disconnection Voltage Threshold Disconnect Detected Disconnect Detected

May 8, Suspend from HS w HS device suspend is initiated when a device sees no activity from upstream port for 3.0ms w Between 3.0 – 3.125ms, device transitions from HS to FS w Device must differentiate between SE0 (reset) and Idle (suspend) w 100 – 875us after reversion to FS, device tests line for SE0 (Reset) vs. FS J (Suspend) w If FS J, device goes into Suspend following FS behaviors

May 8, Timeline for Suspend FS idle (J) HS Idle (device still in HS) μs ms Device reverts to FS Start of Inactivity μSOF HS Hub HS Device D– D+ Device tests bus for FS J and then goes into suspend Start of Suspend Signaling (Hub port goes to FS Idle)

May 8, Resume w For a device suspended while in HS, Resume is a FS K asserted for a minimum of 20ms followed by a transition to SE0 w At end of Resume (while port issuing resume asserts SE0) hub and device transition to HS operation w Since SE0 and HS Idle are equivalent on the bus, there is no “glitching” during this transition w uSOF’s commence in time to prevent a return to suspend

May 8, Timeline for Resume < 3.0 ms Hub Drives SE0 for Two LS Bit Times, Enters HS HS Hub HS Device FS K HS idle μSOF D+ Device sees first activity Start of Resume Signaling D– FS idle > 20 ms Device Resumed In HS < 1.33 μs SE0

May 8, Reset/Speed Detection Protocol w High-speed capable devices are reset by 10ms of continuous SE0 (same as USB 1.1) w During Reset, a high-speed capable device “chIRPs” to the hub w If a USB 2.0 hub detects this chIRP, it completes the handshake by chIRPing back to the device within the Reset w If the handshake is completed during Reset, both hub and device come out of Reset in high-speed mode

May 8, Reset Handshake Signaling w Device chIRP is a ChIRP K (detected with hub’s high-speed receiver) w Device chIRPs by driving current in D- line while leaving D+ pullup in place and leaving terminations inactive w Hub chIRP is a series of alternating ChIRP J’s and K’s w Hub chIRPs by driving current into D+ or D- line w Reference state machines included in Appendix C

May 8, Timeline for Reset μSOF Device ChIRP Hub ChIRP D+ D– ms μs> 1.0 ms < 7.0 ms < 100 μs μs > 10 ms Device ChIRP Start of Reset Device Enters HS < 500 Us After Detecting Hub ChIRP Start of Reset End of Reset End of Hub ChIRP Start of Hub ChIRP μSOF Hub Device SE0SE0SE0 HS idle Device goes into FS Device tests for SE0