PADFRAME Michael Karagounis

Questions & Answers LVDS 1 Question: Do your LVDS circuits meet the specs of the LVDS standard Answer: No, but they are compatible to commercial LVDS circuits 2

LVDS Driver Restrictions Only Thin-Gates Transistors -> max. voltage 1.2-1.5V Maximum output voltage before current source leaves saturation  VDD- 250mV LVDS standard defines a common mode range of 0 – 2.4V for the LVDS receiver  A commercial LVDS receiver (e.g. FPGA input) is able to process the data signal Slide 3 3 3

LVDS Receiver Restrictions Rail-to-Rail Input stage  max. input voltage limited by VDD Option1: To process standard LVDS signal 1.2V +/- 175mV VDD >= 1.375 V Option2: Override Driver Common Mode Voltage Option 3: Use LVDS transceiver chip in test setup Tyhach et al., A 90-nm FPGA I/O Buffer Design With 1.6-Gb/s Data Rate for Source-Synchronous System and 300-MHz Clock Rate for External Memory Interface, IEEE JSSC, Sept. 2005 Slide 4 4 4

Questions & Answers LVDS 2 Does your receiver reach an intermediate state of high current consumption? ( Is your receiver Fail-Safe?) Answer: No, because we bias the receiver input (Yes it is Fail-Safe) 5

Failsafe-Biasing bias voltage close to VDD/2 is defined by resistive divider bias is fed to RX inputs by high ohmic resistors additional high ohmic resistor connected between inverted input & ground introduces voltage difference @ inputs Maxim Application Note 4007, Robust Fail-Safe Biasing for AC-Coupeled Multidrop LVDS Bus, 2007 6

AC Coupled Communication Scheme TX RX CMOS OUT approach allows to study AC-coupled communications scheme  DC – Balancing can be achieved by sending commands with wrong chip id & complementary data during command data transmission breaks 7

Self-Biasing of LVDS Receiver consequence of power-on sequence: LVDS receiver has to be fully functional before the precise reference circuit is available  LVDS receiver has to be self biased LVDS receiver biasing has to be reliable modified version of low voltage beta-multiplier (M1, R2 & R3 have been added) (Baker, CMOS, 2nd edition, IEEE press p. 629) reference current is defined by R1 (R1=R2=R3) circuit has only one dominant pole  easy to compensate addition of transistor M1 gives first order temperature compensation (Friori, A New Compact Temperature compensated CMOS current reference, IEEE Trans. Circ. & Sys., 2005) start-up circuit enforces current flow in the circuit and switches off during normal operation 8

Reference Current vs. Supply Voltage reference current stays stable for VDD > 1.0

Reference Current vs. Temperature variation of referene current < 300nA with temperature

Monte Carlo Simulation Imean=23.7 uA, Isigma=1.3 uA, Imin=17.5uA,Imax=32.5uA

Monte Carlo: RiseTime & Duty Cycle Mean:217ps Sigma:20ps Mean:50.4% Sigma:0.5% Slide 12

STATUS: LVDS circuits OLD NEW LVDS driver Layouts have been adapted to the longer bondpad pitch of production chip (with respect to the test chips)  LVDS driver has now more width & less height Metalization has been changed from LM to DM Design has been ported fom Tripple-Well to T3 substrate isolation option LVDS biasing & failsafe circuits designed & layouted OLD NEW Extraction & simulations of parasitics has not been done yet LVDS driver

Pad Frame 50 Power 22 Digital I/O 13 Analog I/O 21 Probe 128 Overall 133 Maximum External power routing  Possibility to study different powering schemes Pads grouped together to independent supply domains 14

Bond Pads 150um bond pitch Two different bond pad sizes  100um x 200um I/O pads  250um x 200um power pads (corresponds to two I/O pads) ESD devices, vertical M2 & horizontal M3,MQ,MG supply rail routing below the pad Only supply voltage & ground of according supply domain is routed below the pads VDDT3 rail is either connected to dedicated pad (digital domain) or shorted to VDD

Bond Pad Layout Spacer Cell Cut Cell ESD 120um empty for TSV tests ESD devices are located in upper part of the pad lower part has been kept empty for TSV Spacer cells are placed between the pads cut cells seperare pads of different supply domains & provide bus to bus ESD protection ESD 120um empty for TSV tests Analog Input Pad

Question & Answer ESD Question: Do you follow a dedicated ESD strategy? Answer: Yes, we follow the recommendation of the IBM ESD manual! 17

ESD strategy Ground-to-Supply Discharge RC-Clamp Input Pad Bus-to-Bus Protection Output Pad I/O pads are connected via reverse-biased diodes to the supply rails Inputs have seconde diode pair & series resistor  limit max. voltage @ gate of transistor Reverse biased diodes between VDD & GND rails  discharge path from GND to VDD RC-Clamp shorts VDD & GND in case of positive going ESD event  discharge path from VDD to GND Ground busses are protected by antiparallel diodes

Status Padframe All needed pad types have been developed: Supply: Analog VDD Digital VDD VDD 3.3V Wide VDD GND Wide GND Substrate VDDT3 Digital: CMOS IN CMOS OUT LVDS IN LVDS OUT Analog: Analog IN Analog OUT Wide Analog OUT Construction of pad frame ongoing

OLD & BACKUP SLIDES

LVDS Chip Submissions IBM 130nm (LM) UMC 130nm IBM 130nm (DM) 21-Jul-2007: first test chip submitted to UMC 130nm via Europractice mini-asic run  real hardware test of chosen architecture for use in FE-I4 24-Mar-2008: 4 channel LVDS transceiver chip submitted to IBM 130nm (LM) via CERN  for use in a SEU test setup  characterization of new cables and flex types 15-Sep-2008: LVDS driver with tristate option submitted to IBM130nm (DM) via MOSIS IBM 130nm (LM) UMC 130nm IBM 130nm (DM) 2mm 1.8mm 1.5mm 2mm 1.5mm 0.8mm

LVDS Transceiver-Chip Test Setup Type 0 Cable Adapter Type 0 Cable Adapter Biasing developed by A. Eyring 4 x LVDS receiver  CMOS output & CMOS input  LVDS driver Configurable Chain: LVDS receiver  LVDS driver 2x Type 0 cable adapter: LVDS signal  Type 0 cable  termination resistor  LVDS receiver

Measurements LVDS Transceiver Chip Measurement with active differential probe and 100 Ohm termination resistor on PCB @ 1.2V supply LVDS Rx In  LVDS Tx Out @ 320 MHz Clock LVDS RX In  CMOS Out CMOS In  LVDS TX Out Clock-Rate Input Common Mode Voltage Clock-Rate 320MHz 1.05V 320MHz 600mV 160MHz 160MHz 150mV 40MHz 40MHz Increased biased currents needed for LVDS RX to operate @ high frequences & low common mode voltages measured by L. Gonella

LVDS Transceiver-Chip Eye Diagram Test-Setup includes: One – 4 meter twisted pair 36 AWG wire (0.127 mm copper diameter) 160 Mbps data rate Eye pattern is 317mV, need > 200mV No errors @ 150 Mbps or 350 MbpsError rate better than 2*10-13 @ 350 Mbps 350Mbps without cable 160Mbps with cable M. Kocian, D. Nelson, Su Dong SLAC

CMOS Input & Output Buffers Input Buffer Output Buffer Schmitt-Trigger with 200mV hysteresis Cascoded structures have higher snapback voltage Have been used in LVDS-Transceiver chip developed by D. Gnani