Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Slide 1 Spezielle Anwendungen des VLSI – Entwurfs Applied VLSI design Course and contest Results of Phase 2 Nam Pham Van, Sebastian Kruse
Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Change of coefficients Slide 2 Hex F E … F900
Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Change of coefficients Slide 3 Reduce coefficients from 16 bits down to 9 bits Less calculations by multiply operation Hex F9 02 1E … F9
Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Change of coefficients Slide 3 Hex F9 02 1E Hex Binary F E Reduce coefficients from 16 bits down to 9 bits Less calculations by multiply operation Symmetric layout of coefficients Only the first 5 coefficients have to compute
Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Change of coefficients Slide 3 Reduce coefficients from 16 bits down to 9 bits Less calculations by multiply operation Symmetric layout of coefficients Only the first 5 coefficients have to compute Use of CSD-Recoding Reducing of non-zero digits Hex Binary CSD (Canonical Sign Digit) F E
Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Change of coefficients Slide 3 Reduce coefficients from 16 bits down to 9 bits Less calculations by multiply operation Symmetric layout of coefficients Only the first 5 coefficients have to compute Use of CSD-Recoding Reducing of non-zero digits Hex Binary CSD (Canonical Sign Digit) F E
Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Change of coefficients Slide 3 Reduce coefficients from 16 bits down to 9 bits Less calculations by multiply operation Symmetric layout of coefficients Only the first 5 coefficients have to compute Use of CSD-Recoding Reducing of non-zero digits Hex Binary CSD (Canonical Sign Digit) F E
Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Change of coefficients Slide 3 Reduce coefficients from 16 bits down to 9 bits Less calculations by multiply operation Symmetric layout of coefficients Only the first 5 coefficients have to compute Use of CSD-Recoding Reducing of non-zero digits Hex Binary CSD (Canonical Sign Digit) F E
Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Change of coefficients Slide 3 Reduce coefficients from 16 bits down to 9 bits Less calculations by multiply operation Symmetric layout of coefficients Only the first 5 coefficients have to compute Use of CSD-Recoding Reducing of non-zero digits Hex Binary CSD (Canonical Sign Digit) F E
Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Change of coefficients Slide 3 Reduce coefficients from 16 bits down to 9 bits Less calculations by multiply operation Symmetric layout of coefficients Only the first 5 coefficients have to compute Use of CSD-Recoding Reducing of non-zero digits Hex Binary CSD (Canonical Sign Digit) F E
Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Phase 2 – direct form II Slide 4 Direct form I Direct form II h(0) h(1) h(N-2) h(N-1) z -1 y(i) x(i) 0 h(0) h(1) h(N-2) h(N-1) z -1 0 x(i) y(i)
Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Pipeline stages Slide 5 By using direct form II 8 pipeline stages are implemented Reducing of unnecessary bits 10 bit RCA for summation and multiplication 11 bit & 16 bit RCA for multiplication (5’th coefficient only) Separate the 5’th calculation into two pipeline stages
Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Filter response Slide 6
Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Results Slide 7 Mandatory values for FPGA Phase 1 (Synthese) Phase 2 (Place & Route) Frequency - f69,911 MHz 425,170 MHz Area - A (# of LUT-FF Pairs) # Pipeline Stages18 Metric (MHz / LUT-FF Pairs) [0,032][3,900]
Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Future improvements Change type of adder (phase 3) Brent Kung adder Han Carlson adder Carry skip adder Only do an addition for important digits Summation compression (Wallace tree) Carry save representation Slide 8
Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Thank you for your attention! Slide 9