Penn ESE370 Fall DeHon 1 ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 33: November 20, 2013 Crosstalk

Today Crosstalk –How arise –Consequences –Magnitude –Avoiding Penn ESE370 Fall DeHon 2

Capacitance There are capacitors everywhere Already talked about –Wires as capacitors –Capacitance between terminals on transistor Penn ESE370 Fall DeHon 3

Miller Effect For an inverting gate Capacitance between input and output must swing 2 V high Or…acts as double- sized capacitor Penn ESE370 Fall DeHon 4

Capacitance Everywhere Potentially a capacitor between any two conductors –On the chip –On the package –On the board All wires –Package pins –PCB traces –Cable wires –Bit lines Penn ESE370 Fall DeHon 5

Capacitor Dependence Decrease with conductor separation Increase with size Depends on dielectric Penn ESE370 Fall DeHon 6

Parallel Wires Parallel-plate capacitance between wires Penn ESE370 Fall DeHon 7

Wire Capacitance Changes in voltage on one wire may couple through capacitance to another Penn ESE370 Fall DeHon 8

Consequences Qualitative First Penn ESE370 Fall DeHon 9

Wire step response Step response for isolated wire? Penn ESE370 Fall DeHon 10

Driven Wire What happens to a driven wire? –Wire switches –Neighbors driven but not switch switch Penn ESE370 Fall DeHon 11

Driven Wire Can this be a problem? What if victim is: –Clock line –Asynchronous control –Non-clock used in synchronous system Outputs sampled at clock edge Penn ESE370 Fall DeHon 12

Undriven Wire What happens to undriven wire? Where do we have undriven wires? Penn ESE370 Fall DeHon 13

Clocked Logic CMOS driven lines Clocked logic Willing to wait to settle Impact is solely on delay –May increase delay of transitions Penn ESE370 Fall DeHon 14

Magnitude Quantitative Penn ESE370 Fall DeHon 15

How large is the noise? V 1 transitions from 0 to V? Penn ESE370 Fall DeHon 16

How large is the noise? V 1 transitions from 0 to V Penn ESE370 Fall DeHon 17

Noise Magnitude Penn ESE370 Fall DeHon 18

SPICE C 1 =10pF, C 2 =20pF Penn ESE370 Fall DeHon 19

Good (?) Capacitance High capacitance to ground plane –Limits node swing from adjacent conductors Penn ESE370 Fall DeHon 20

Driven Line What happens when victim line is driven? Penn ESE370 Fall DeHon 21

Driven Line Driven line –Recovers with time constant: R 2 (C 1 +C 2 ) Penn ESE370 Fall DeHon 22

Spice : R 2 =1K, C 1 =10pF, C 2 =20pF Penn ESE370 Fall DeHon 23

Magnitude of Noise on Driven Line Magnitude of diversion depends on relative time constants –   <<  2 –   >>  2 –   ~=  2 Penn ESE370 Fall DeHon 24

Magnitude of Noise on Driven Line Magnitude of diversion depends on relative time constants –   <<  2 full diversion, then recover –   ~=  2 –   >>  2 Charge capacitor faster than line 1 can change –little noise Penn ESE370 Fall DeHon 25

Spice: C 1 =1pF, C 2 =2pF Penn ESE370 Fall DeHon 26

Switching Line with Finite Drive What impact does the presence of the non switching line have on the switching line? –All previous questions were about non-switching –Note R on switching Penn ESE370 Fall DeHon 27

Simultaneous Transition What happens if lines transition in opposite directions? Penn ESE370 Fall DeHon 28

Simultaneous Transition What happens if transition in opposite directions? –Must charge C 1 by 2V –Or looks like 2C 1 between wires Penn ESE370 Fall DeHon 29

Simultaneous Transition What happens if lines transition in same direction? Penn ESE370 Fall DeHon 30

Simulation V2 switching at ¼ frequency of V1 No crosstalk reference case where no V2 Penn ESE370 Fall DeHon 31

Victimization Setup Penn ESE370 Fall DeHon 32

Crosstalk Victim Simulations Penn ESE370 Fall DeHon 33

Where Arise Penn ESE370 Fall DeHon 34

Cables and PCB Wires Penn ESE370 Fall DeHon 35 Source;

Printed Circuit Board Penn ESE370 Fall DeHon 36 Source:

37 Interconnect Cross Section ITRS 2007 Penn ESE370 Fall DeHon 37

IC Metalization Penn ESE370 Fall DeHon 38 Source:

Penn ESE370 Fall DeHon Standard Cell Area invnand3 All cells uniform height Width of channel determined by routing Cell area Identify the full custom and standard cell regions on 386DX die 39

Wires Will be capacitively coupled to many adjacent wires of varying degrees Penn ESE370 Fall DeHon 40

bit lines, word lines Penn ESE370 Fall DeHon 41 Source: bitline wordline

Addressing Penn ESE370 Fall DeHon 42

What can we do? How can we reduce? Penn ESE370 Fall DeHon 43

What can we do? Orthogonal routing layers –Avoid parallel coupling vertically Widen spacing between wires –Particularly critical path wires Limit length two wires run in parallel Separate with power planes Separate with ground/power wires Penn ESE370 Fall DeHon 44

Idea Capacitance is everywhere Especially between adjacent wires Will get “noise” from crosstalk Clocked and driven wires –Slow down transitions Undriven wires voltage changed Can cause spurious transitions Penn ESE370 Fall DeHon 45

Admin In lab on Friday –Please read lab handout in advance Project due Tuesday Penn ESE370 Fall DeHon 46