ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU Final project Speaker:Aeag ( 柯鴻洋 ) Advisor: Prof. Andy Wu 2003/05/29

ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU pp /05/31  Use fig as an example to design your 1-bit Edge- triggered DFF. Cascade four DFF ’ s to form a 4-bit Data register.  Cascade four 1-bit Full-adder(from Hw3) to form a 4-bit Ripple adder.  Use the 4-bit Ripple Adder and 4-bit Register to design an accumulator that can calculate The serial input are 1,2,3,4,5 one data at a clock. Goal

ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU pp /05/31 Block diagram 4-bit full-adderD-FF clk reset Input sum

ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU pp /05/31 Ex1 for D-FF circuit Ref [1]

ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU pp /05/31 Ex1 for D-FF circuit cont. Ref [1]

ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU pp /05/31 Ex2 for D-FF circuit Ref [1]

ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU pp /05/31 Waveform for D-FF Ref [1]

ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU pp /05/31 Ex for 1-bit Accumulator Ref [2]

ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU pp /05/31 Expected Waveform Ref [2]

ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU pp /05/31 Spice simulation Ref [2]

ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU pp /05/31 Hand in  Using spice simulation to verify the function of 4- bit Ripple adder and 4-bit d ata register respectively.  A plot of the layout for 4-bit Ripple adder and 4- bit data register respectively.  Try to estimate the fasting clock rate. Use SPICE to simulate the speed of your circuit.

ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU pp /05/31 Hand in cont.  What would be the critical path of the accumulator design? Please discuss.  According requirement (3) to combine the circuit of (1) and (2) to form an accumulator, you need to hand in the accumulator layout. And the accumulator or the design flow from (layout=>DRC=>LVS) must be verified correctly. (DRC and LVS ’ s report should be no errors, and result should been contained in your final report)

ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU pp /05/31 Reference  [1] “CMOS Integrated Circuits: Analysis and Design,” 3 rd Ed., by Sung-Mo Kang and Yusuf Leblebici, McGraw-Hill,  [2]

ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU pp /05/31 Good luck! Thank you!