1 i386 Memory Management Professor Ching-Chi Hsu 1998 年 4 月

2 Registers (1) general registers –eight 32-bit general-purpose registers(eax,ebx,ecx,edx,ebp,esp,esi,edi) –ebp is calculated automatically in current stack segment,or explicitly specified to index into segments via other segment segment registers –six 16-bit special-purpose registers(cs,ds,ss,es,fs,gs) cs : code segment in which the text lies ds,fs,gs : data segment ss : stack segment instruction register –instruction pointer register(eip)

3 Registers (2) system registers –flag register (eflags) –mem-mgr registers gdtr & ldtr : global & local descriptor table register,point to the segment descriptor table idtr : interrupt descriptor table registers,point to a table of entry points for interrupt handlers tsr : task register,point to the pcb of current task –control registers cr0 : system control flags which control or indicate conditions that apply to the system as a whole,not to an individual task –PG(paging bit 31) : using page table to translate linear address into physical address –PE(protection enable bit 0) : setting PE cause the processor executing in protected mode,otherwise real-address mode cr2 : handling page faults when PG is set,it contains the linear address that triggers the fault cr3 : pointing to page table directory when PG is set –debug register : bring advanced debugging abilities to the –test register : to enable confidence testing of the TLB

4 Memory Management (1) Segment translation –in which a logical address is converted to a linear address page translation (optional) –in which a linear address is converted to a physical address to perform translation,the following data structure are used –descriptors –descriptor tables –selectors –segment registers

5 Memory Management (2) selector offset logical address segment translation PG? dir page offset paging enable page translation 0 31 linear address physical address paging disable

6 Segment Translation (1) selectoroffset descriptor table segment descriptor base address + dir pageoffset linear address

7 Segment Translation (2) descriptors –providing the processor with the data it needs to map a logical address into a linear address –Base : defines the location of the segment within 4 gigabytes –Limit : defines the size of segment (20 bits) reset G bit : in unit of one byte,a limit of up to 1 megabytes set G bit : in unit of 4 kilobytes,a limit of up to 4 gigabytes –Granularity bit : specifies the units with which the LIMIT field is interpreted –Type : distinguishes between various kinds of descriptors –DPL : descriptor privilege level,for protection mechanism –Segment Present bit : the segment is presented or not –Access bit : processor set the bit when accessed

8 Segment Translation (3) Base G X 0 AVLAVL limit p DPI 1 TYPE A base segment base segment limit Accessed abailable for use by systems programmers descriptor privilege level granularity segment present A AVL DPL G P

9 Segment Translation (4) descriptor tables –the table is simply a memory array of 8-byte entries that contains descriptors –two kinds of tables GDT : global descriptor table LDT : local descriptor table –the table may contains up to 8192 descriptors,64K in size –the first entry of GDT (index=0) is not used by the processor –LGDT & LLDT instructions load the base address and limit into gdt & ldt

10 Segment Translation (5) (unused) GDTRLDTR Global descriptor table Local descriptor table M N+3 N+2 N+1 N 0 M N+3 N+2 N+1 N 0

11 Segment Translation (6) Selectors –the selector portion of a logical address identifies a descriptor by specifying a descriptor table and indexing a descriptor within that table –Index:select one of 192 descriptors in a descriptor table.the processor multiplies this index value by 8 (the length of a descriptor) and adds the result to the base of the descriptor table to access the appropriate segment descriptor in the table. –Table Indicator : specifies to which descriptor table the selector refers.a zero indicates the GDT;a one indicates the LDT –Requested Privilege Level : for protection mechanism T index 150 RPL requested privilege level T1 table indicator

12 Segment Translation (7) Segment registers –80386 stores information from descriptors in segment register,thereby avoiding consult a descriptor table every time it accessed memory –each segment register has a “visible” portion and an “invisible” portion;the visible part are manipulated as if there were 16-bit registers,the invisible part are manipulated by processor. CS DS ES SS ES FS 16-bit visible selector hidden descriptor

13 Page Translation A page frame is a 4K-byte unit of contiguous addressed of physical memory linear address –a linear address refers indirectly to a physical address by specifying a page table,a page within that table and an offset within that page. –It is a two level page table –DIR : an index into a page directory –PAGE : an index into the page table determined by the page directory –OFFSET : point to a byte within the page determined by the page table

14 Page Translation Page tables –an array of 32-bit page specifies –it is itself a page and therefore contains 4K-byte of memory or at most 1K 32-bit entries. –The page directory addressed up to 1K page tables of the second level –a page of second level address up to 1K pages –so one page directory can address 1M pages that is 4G-byte in size –the physical address of page directory is stored in CR3 DIRPAGEOFFSET

15 Page Translation Page table entries –page frame address : pages are 4K aligned,the low-order 12 bits are zero –present bit indicates whether a page table entry can be used in address translation when P=0 i n either level,the entry is not valid for address translation, and the rest of the entry is available for software use if P=0 in either level of page tables when attempt is made to use a page-table entry for address translation, the processor signals a page exception –accessed and dirty bits provide data about page usage in both level the processor set accessed bit before a read or write operation the dirty bits of second level page table are set before a write operation, but the dirty bits in directory entries are undefined. –Protection when the processor is at supervisor mode, all pages are readable and writable when at user mode, only the pages belongs to user mode and with r/w bits set are writable.

16 Page Translation padPage frame address avail 0 w/r s/u Ppresent r/wread/write u/suser/supervisor aaccessed ddirty availavailable for systems programmer use note : 0 indicates reserved

17 Page Translation dirpageoffset page directory dir entry page table dir entry page frame physical address cr3