FET Biasing 1

Introduction For the JFET, the relationship between input and output quantities is nonlinear due to the squared term in Shockley’s equation. For the JFET, the relationship between input and output quantities is nonlinear due to the squared term in Shockley’s equation. Nonlinear functions results in curves as obtained for transfer characteristic of a JFET. Nonlinear functions results in curves as obtained for transfer characteristic of a JFET. Graphical approach will be used to examine the dc analysis for FET because it is most popularly used rather than mathematical approach Graphical approach will be used to examine the dc analysis for FET because it is most popularly used rather than mathematical approach The input of BJT and FET controlling variables are the current and the voltage levels respectively The input of BJT and FET controlling variables are the current and the voltage levels respectively 2

Introduction JFETs differ from BJTs: Nonlinear relationship between input (V GS ) and output (I D ) JFETs are voltage controlled devices, whereas BJTs are current controlled 3

Introduction Common FET Biasing Circuits JFET – Fixed – Bias – Self-Bias – Voltage-Divider Bias Depletion-Type MOSFET – Self-Bias – Voltage-Divider Bias Enhancement-Type MOSFET – Feedback Configuration – Voltage-Divider Bias 4

General Relationships For all FETs: For JFETs and Depletion-Type MOSFETs: For Enhancement-Type MOSFETs: 5

Fixed-Bias Configuration The configuration includes the ac levels Vi and Vo and the coupling capacitors. The configuration includes the ac levels Vi and Vo and the coupling capacitors. The resistor is present to ensure that Vi appears at the input to the FET amplifier for the AC analysis. The resistor is present to ensure that Vi appears at the input to the FET amplifier for the AC analysis. 6

Fixed-Bias Configuration For the DC analysis, For the DC analysis, Capacitors are open circuits Capacitors are open circuits and and The zero-volt drop across R G permits replacing R G by a short-circuit The zero-volt drop across R G permits replacing R G by a short-circuit 7

Fixed-Bias Configuration Investigating the input loop I G =0A, therefore I G =0A, therefore V RG =I G R G =0V V RG =I G R G =0V Applying KVL for the input loop, Applying KVL for the input loop, -V GG -V GS =0 V GG = -V GS It is called fixed-bias configuration due to V GG is a fixed power supply so V GS is fixed It is called fixed-bias configuration due to V GG is a fixed power supply so V GS is fixed The resulting current, The resulting current, 8

Investigating the graphical approach. Investigating the graphical approach. Using below tables, we Using below tables, we can draw the graph can draw the graph 9 V GS IDIDIDID 0 I DSS 0.3V P I DSS /2 0.5 I DSS /4 VPVPVPVP0mA

The fixed level of V GS has been superimposed as a vertical line at The fixed level of V GS has been superimposed as a vertical line at At any point on the vertical line, the level of V G is -V GG --- the level of I D must simply be determined on this vertical line. At any point on the vertical line, the level of V G is -V GG --- the level of I D must simply be determined on this vertical line. The point where the two curves intersect is the common solution to the configuration – commonly referrers to as the quiescent or operating point. The point where the two curves intersect is the common solution to the configuration – commonly referrers to as the quiescent or operating point. The quiescent level of I D is determine by drawing a horizontal line from the Q-point to the vertical I D axis. The quiescent level of I D is determine by drawing a horizontal line from the Q-point to the vertical I D axis. 10

Output loop Output loop 11

Example Determine V GS Q, I D Q, V DS, V D, V G, V S Determine V GS Q, I D Q, V DS, V D, V G, V S 12

Exercise Determine I D Q, V GS Q, V DS, V D, V G and V S Determine I D Q, V GS Q, V DS, V D, V G and V S 13

Self Bias Configuration The self-bias configuration eliminates the need for two dc supplies. The self-bias configuration eliminates the need for two dc supplies. The controlling V GS is now determined by the voltage across the resistor R S The controlling V GS is now determined by the voltage across the resistor R S 14

For the indicated input loop: Mathematical approach: rearrange and solve. 15

Graphical approach Graphical approach Draw the device transfer characteristic Draw the device transfer characteristic Draw the network load line Draw the network load line Use to draw straight line. Use to draw straight line. First point, First point, Second point, any point from I D = 0 to I D = I DSS. Choose Second point, any point from I D = 0 to I D = I DSS. Choose the quiescent point obtained at the intersection of the straight line plot and the device characteristic curve. the quiescent point obtained at the intersection of the straight line plot and the device characteristic curve. The quiescent value for I D and V GS can then be determined and used to find the other quantities of interest. The quiescent value for I D and V GS can then be determined and used to find the other quantities of interest. 16

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For output loop For output loop Apply KVL of output loop Apply KVL of output loop Use I D = I S Use I D = I S 18

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Example Determine V GS Q, I D Q,V DS,V S,V G and V D. Determine V GS Q, I D Q,V DS,V S,V G and V D. 20

Example Determine V GS Q, I D Q, V D,V G,V S and V DS. Determine V GS Q, I D Q, V D,V G,V S and V DS. 21

Voltage-Divider Bias The arrangement is the same as BJT but the DC analysis is different The arrangement is the same as BJT but the DC analysis is different In BJT, I B provide link to input and output circuit, in FET V GS does the same In BJT, I B provide link to input and output circuit, in FET V GS does the same 22

Voltage-Divider Bias The source V DD was separated into two equivalent sources to permit a further separation of the input and output regions of the network. The source V DD was separated into two equivalent sources to permit a further separation of the input and output regions of the network. I G = 0A,Kirchoff’s current law requires that I R1 = I R2 and the series equivalent circuit appearing to the left of the figure can be used to find the level of V G. I G = 0A,Kirchoff’s current law requires that I R1 = I R2 and the series equivalent circuit appearing to the left of the figure can be used to find the level of V G. 23

Voltage-Divider Bias V G can be found using the voltage divider rule : V G can be found using the voltage divider rule : Using Kirchoff’s Law on the input loop: Using Kirchoff’s Law on the input loop: Rearranging and using ID =IS: Rearranging and using ID =IS: Again the Q point needs to be established by plotting a line that intersects the transfer curve. Again the Q point needs to be established by plotting a line that intersects the transfer curve. 24

Procedures for plotting Plot the line: By plotting two points: V GS = V G, I D =0 and V GS = 0, I D = V G /R S 2. Plot the transfer curve by plotting I DSS, V P and calculated values of I D. 3. Where the line intersects the transfer curve is the Q point for the circuit.

Once the quiescent values of I DQ and V GSQ are determined, the remaining network analysis can be found. Once the quiescent values of I DQ and V GSQ are determined, the remaining network analysis can be found. Output loop: Output loop: 26

Effect of increasing values of R S 27

Example Determine I D Q, V GS Q, V D, V S, V DS and V DG. Determine I D Q, V GS Q, V D, V S, V DS and V DG. 28

Example Determine I D Q, V GS Q, V DS, V D and V S Determine I D Q, V GS Q, V DS, V D and V S 29