SoC Design Flow and Tools CADENCE NCLAUNCH TUTORIAL 2003/10/6

Outline Introduction Setting up the environment Invoking NCLaunch Components of NCLaunch Examples LAB Reference

Introduction NCLaunch is a graphical user interface that helps you manage large design projects and lets you configure and launch your Cadence simulation. It help user simulate Verilog, VHDL, or mixed-language design.

Setting up the environment Creating a new directory under your home directpry to store all your vhdl/verilog design. /home/username/ >mkdir test It is important that you must have two files in this new directory before you begin working. These are the cds.lib file and the hdl.var file. cds.lib SOFTINCLUDE $CDS_INST_DIR/tools/inca/files/cds.lib DEFINE test /home/username/test hdl.var SOFTINCLUDE $CDS_INST_DIR/tools/inca/files/hdl.var DEFINE work test

Invoking NCLaunch Do with thefollowing command in a shell windows: >cd /usr/local/cadence/ldv5.0/tools/bin >nclaunch & (若可在自己的工作目錄下(home/username/)直接打nclaunch &也可以)

Components of NCLaunch Menu Bar Toolbar Icons File Browser Design Area Console Window

Components of NCLaunch b c d e f g h a. Edit File. By selecting a file and clicking this icon, a text editor (defined in your Preferences) appears with the files contents to review or modify. b. Refresh. Updates your browsers with any changes. c. Compile VHDL Files (multi-step only). Compiles selected VHDL files that will appear as design units under your work library in the Library Browser. d. Compile Verilog Files (multi-step only). Compiles selected Verilog files that will e. Elaborate Files (multi-step only). By selecting the top level design unit and clicking this icon, your design will be elaborated. f. Run Simulation. Starts a simulation of your selected design. g. Browse Logfiles. Launches the NCBrowse message browser to analyze selected log files. h. Waveform Viewer. Starts a session of the waveform viewer tool with selected database files.

Examples Assume that we have two vhdl file (trial.vhd and test_trial.vhd) and cds.lib file and hdl.var file in the directory (/home/username/test). Step 1: Set Design Directory

Choose your design directory. Load the library file (load the cds.lib file that haven edited in your design directory). Set Work Library name as same as your directory name (set in cds.lib and hdl.var).

Assume that we have two VHDL file (trial. vhd and test_trial Assume that we have two VHDL file (trial.vhd and test_trial.vhd) and cds.lib file and hdl.var file in the directory (/home/username/test). Step 2: Compiler the two VHDL files then, it will produce two file

After Step 2, it will produce two file. (trial and test_trial) In this Step, you can also use the button in the toolbar.

Step 3: Elaborating the Design type command in the console windows >ncelab my_lib.top:behav nclaunch>ncelab test.trial:trial_rtl nclaunch>ncelab test.test_trial:tb_arch After it, the elaborated design hierarchy is stored in a simulation snapshot file, which is used by the simulator.

Step 4: Initiating the simulation type command in console window nclaunch>ncsim –gui test_trial & before invoking the Signalscan, it is important to select the signals to display on the waveform. Choose Select -> Signals from the menu of the simulator.

To invoke the Signal scan click on the button in the upper right corner.

LAB 1.Run this example throughout. 2.The waveform for the time range in 100ns, 250ns, 300ns. Mail three pictures to TA. 3.deadline: 10/13 12:00PM 4. http://embedded.cs.ccu.edu.tw/~suner/codesign.htm

Reference 1. Affirma NC VHDL Simulator Tutorial usr/local/cadence/ldv5.0/doc/ncvhdltut/ncvhdltut.pdf. 2. NCLaunch User Guide usr/local/cadence/ldv5.0/doc/nclaunch/ nclaunch.pdf. 3. Affirma NC VHDL Simulator Help usr/local/cadence/ldv5.0/doc/ncvhdl/ncvhdl.pdf. 4. Affirma NC Verilog Simulator Help usr/local/cadence/ldv5.0/doc/ ncvlog/ncvlog.pdf. 5. SignalScan Waves User Guide usr/local/cadence/ldv5.0/doc/ signalscanwaves/ signalscanwaves.pdf. 6. Cadence VHDL/Verilog Simulation Guide and Tutorial