Memory and Storage

Computer Memory Processor registers – Temporary storage locations within the CPU – Examples Instruction register – holds the instruction that the CPU is working on Program Counter – holds the address of the next instruction to be fetched

Computer Memory Continued Cache Memory Small memory between the CPU and Primary memory – Classes L1 – on the CPU chip – small capacity 8Kb – 256 KB L2 (64Kb – 4MB) – Newer chips have advanced transfer cache on the chip – Older chips use off chip cache on the Motherboard L3 – off chip cache if L2 is on the chip

Computer Memory Continued Primary memory – RAM – random access memory that can be read and written Textbook refers to this as RWM –read/write memory – ROM – random access memory that can only be read

Computer Memory Continued Secondary Memory – Direct Access Devices hard drive floppy disk DVD ZIP drives CD-Rom, CD-RW, CD-W – Serial Access devices Tape drives

Memory Parameters Capacity – Maximum number of bytes or words that it can store Access time – Time taken by the memory module to access data after an address is provided Data Transfer Rate – Number of bits per second that can be read out of memory Cycle Time – Measure of how often the memory can be accessed Cost – Price of memory per bit/byte

Access time Ram or Rom - how long after an address is provided that the data is available at the Memory Buffer Register. The access time is the same for all memory locations on the same chip. Disk access - takes into account rotation delay to get to the proper sector(based on the rpm of the disk), Head movement to get to the proper track

Memory hierarchy as far as speed and cost on page 155

Ram es.htm es.htm static – each memory cell storage element is a flip flop – faster than dynamic but more costly – takes up more room on a chip per bit – used in cache memory dynamic – each memory cell storage element is a capacitor or a transistor acting like a capacitor – needs refresh circuitry – slower but less expensive than static – used in regular Ram in your PC

Static Ram memory cell on page 157 read (see what the contents are) write (change the contents)

Dynamic Ram page 161 and 162

Decoding linear decoding page coincident decoding page 160 and 162

ROM explained pg 163

memory addressing number of words = 2 ^ number of addressees 1 address for 2 words 2 addresses for 4 words 1024 = 2 ^10 -> 10 addresses for 1K words 2048 = 2 ^11 -> 11 addresses for 2K words

Memory system design using IC’s pg increasing the number of words increasing the number of bits