Combinational Logic Design Process 1. Understand the Problem what is the circuit supposed to do? write down inputs (data, control) and outputs draw block diagram or other picture 2. Formulate the Problem in terms of a truth table or other suitable design representation truth table, Boolean algebra, etc. 3. Choose Implementation Target PAL, PLA, Mux, Decoder, Discrete Gates 4. Follow Implementation Procedure K-maps, Boolean algebra

Process Line Control Example Statement of the Problem Rods of varying length (+/-10%) travel on conveyor belt Mechanical arm pushes rods within spec (+/-5%) to one side Second arm pushes rods too long to other side Rods too short stay on belt 3 light barriers (light source + photocell) as sensors Design combinational logic to activate the arms Understanding the Problem Inputs are three sensors, outputs are two arm control signals Assume sensor reads "1" when tripped, "0" otherwise Call sensors A, B, C Draw a picture!

Process Line Control Example (cont.) Where to place the light sensors A, B, and C to distinguish among the three cases? Assume that A detects the leading edge of the rod on the conveyor

Process Line Control Example (cont.) A to B distance place apart at specification - 5% A to C distance placed apart at specification +5%

Process Line Control Example (cont.)

Logical Function Unit Statement of the Problem: C0 C1 C2 F Comments 0 0 0 1 Always 1 0 0 1 A + B logical OR 0 1 0 A*B logical NAND 0 1 1 A xor B logical XOR 1 0 0 A xnor B logical XNOR 1 0 1 A*B logical AND 1 1 0 A+B logical NOR 1 1 1 0 always 0 3 control inputs: C0, C1, C2 2 data inputs: A, B 1 output: F Similar to the main computation unit in a Microprocessor

Logical Function Unit (cont.) C0 C1 C2 A B F 0 0 0 0 0 1 0 0 0 0 1 1 0 0 0 1 0 1 0 0 0 1 1 1 0 0 1 0 0 0 0 0 1 0 1 1 0 0 1 1 0 1 0 0 1 1 1 1 0 1 0 0 0 1 0 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 1 0 0 1 1 0 0 0 0 1 1 0 1 1 0 1 1 1 0 1 0 1 1 1 1 0 1 0 0 0 0 1 1 0 0 0 1 0 1 0 0 1 0 0 1 0 0 1 1 1 1 0 1 0 0 0 1 0 1 0 1 0 1 0 1 1 0 0 1 0 1 1 1 1 1 1 0 0 0 1 1 1 0 0 1 0 1 1 0 1 0 0 1 1 0 1 1 0 1 1 1 0 0 0 1 1 1 0 1 0 1 1 1 1 0 0 1 1 1 1 1 0 Formulate as a truth table Choose implementation technology 4 TTL packages: 4 x 2-input NAND 4 x 2-input NOR 2 x 2-input XOR 8:1 MUX A B A B A B + 5 V D D 1 D 2 D 3 D 4 D 5 D 6 D 7 S C 2 E N 8:1 Mux S 1 C 1 Q O S 2 C F

Logical Function Unit (cont.) Follow implementation procedure C 1 2 A B 00 01 11 10 C =0 00 1 1 F = C2' A' B' + C0' A B' + C0' A' B + C1' A B 01 1 1 1 1 11 1 1 5 gates, 5 inverters Also four packages: 4 x 3-input NAND 1 x 4-input NAND Alternative: PAL/PLA single package 10 1 1 1 1 C 1 2 A B 00 01 11 10 C =1 00 1 1 01 11 1 1 10

Combinational vs. Sequential Logic X Network implemented from logic gates. The presence of feedback distinguishes between sequential and combinational networks. 1 Z 1 2 m X 2 Logic Network - - X n Combinational logic no feedback among inputs and outputs outputs are a pure function of the inputs e.g., seat belt light: (Dbelt, Pbelt, Passenger) mapped into (Light) Dbelt Logic Circuit Seat Belt Light Pbelt Passenger

Circuit Timing Behavior Simple model: gates react after fixed delay A B C D E F A B C D E F 1 1

Hazards/Glitches Circuit can temporarily go to incorrect states Must filter out temporary states Copilot Autopilot Request B A Pilot in Charge? Autopilot Engaged Pilot Autopilot Request C CAR PIC PAR A B C AE

Safe Sequential Circuits Clocked elements on feedback, perhaps outputs Clock signal synchronizes operation Clocked elements hide glitches/hazards X 1 2 n Z 1 2 m - Logic - Network Clock Clock Data Compute Valid Compute Valid Compute