Chapter 6 Know commonly used combinational subcircuits –Multiplexers –Decoders –Encoders Know VHDL constructs used to define combinational circuits

Multiplexers f s w 0 w f s w 0 w 1 2 to 1 Multiplexer f s w 0 w 1

f s 1 w 0 w 1 s 0 w 2 w 3 f s 1 w 0 w w 0 w 1 s 0 w 2 w fs 1 0 s 0 w 2 w 3 4 to 1 Multiplexer

Using 2-to-1 multiplexers to build a 4-to-1 multiplexer. 0 w 0 w w 2 w f 0 1 s 1 s w 0 w fs 1 0 s 0 w 2 w 3

Synthesis of Logic Functions Using Multiplexers fw 1 0 w XOR

Shannon’s Expansion Any Boolean function can be written f(w1,w2,…wn) = w1f(0,w2,…,wn) + w1f(1,w2,…, wn) f=w1w2 + w1w3 + w2w3 = w1(w2w3) + w1(w2+w3) –!w1(0w2 + 0w3 + w2w3) + w1(1w2 + 1w3 + w2w3) –!w1(w2w3) + w1(w2 + w3 + w2w3) 5a x0 = 0, 6a x1 = x –!w1(w2w3) + w1(w2 + w3) through successive application of 13a x + xy = x Shannon provided yet another tool for logic synthesis

Decoders y 0 w 1 0 w 0 xx En y y y w 0 y 0 w 1 y 1 y 2 y 3 A 2-to-4 decoder

w 1 w 0 y 0 y 1 y 2 y 3 En

3-to-8 Decoder using two 2-to-4 decoders w 2 w 0 y 0 y 1 y 2 y 3 w 0 En y 0 w 1 y 1 y 2 y 3 w 0 y 0 w 1 y 1 y 2 y 3 y 4 y 5 y 6 y 7 w 1

? w 1 w 0 w 0 y 0 w 1 y 1 y 2 y 3 w 2 w 3 f s 0 s 1 1

w 1 w 0 w 0 y 0 w 1 y 1 y 2 y 3 f s 0 s 1 1 w 2 w 3

Demultiplexers Using a decoder –En is data input –w1,w0 select which output is active –y3,…,y0 are data outputs y 0 w 1 0 w 0 xx En y y y

Encoders Assumes only one input active w 3 y 1 0 y 0 w 1 w w w w y 0 w 2 w 3 y 1

Priority Encoders w0 lowest priority w3 highest priority zindicates inputs active y1, y0 binary number of highest priority active d w 0 y 1 d y z 1 x x 0 x w x 0 x w x w

Code Converters 3-to-8 binary decoder 8-to-3 binary encoder BCD-to-7-segment decoder ce w 0 a w 1 b c d w 2 w 3 e f g a g bf d w 0 a 1 b w w w c d e f g