Safely Exploiting Multithreaded Processors to Tolerate Memory Latency

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Presentation transcript:

Safely Exploiting Multithreaded Processors to Tolerate Memory Latency in Real-Time Systems Title Slide Ali El-Haj-Mahmoud and Eric Rotenberg Center for Embedded Systems Research (CESR) Electrical & Computer Engineering North Carolina State University

Embedded Processor Trends More demanding applications and user expectations Higher frequency ARM-11 (0.13µ): 500 MHz ARM-11 (0.10µ): 1 GHz Processor-memory speed gap El-Haj-Mahmoud © 2004 CASES 2004

How to capitalize on higher frequency? Memory Wall How to capitalize on higher frequency? El-Haj-Mahmoud © 2004 CASES 2004

Multithreading Switch-on-event coarse-grain multithreading Multiple register contexts for fast switching Switch to alternate task when current task accesses memory Overlap memory accesses with computation But what about multithreading in hard-real-time? Require analyzability Cannot rely on dynamic schemes El-Haj-Mahmoud © 2004 CASES 2004

Exploiting Multithreading in Hard-Real-Time Systems Safety Guarantee all tasks meet deadlines (worst-case) Statically bound overlap under all scenarios Tractability Confirm/disconfirm schedulability mathematically using closed-form tests Consider each task individually El-Haj-Mahmoud © 2004 CASES 2004

Classic Real-Time Scheduling Example: Earliest Deadline First (EDF) periodA time Task A A1 A2 release A1 deadline A1 release A2 periodB Task B B1 B2 B3 B4 release B1 deadline B1 release B2 EDF schedulability test EDF B1 A1 B2 B3 A2 B4 Utilization-based schedulability test No need to construct the schedule a priori El-Haj-Mahmoud © 2004 CASES 2004

Performance vs. Tractability Performance: Memory overlap Tractability: Closed-form schedulability test Only basic parameters of tasks are known WCET = C + M (from conventional WCET analysis) Period = deadline A B M El-Haj-Mahmoud © 2004 CASES 2004

EDF (Classic Real-Time): Low Performance but Tractable DEADLINE MISSED Memory overlap: No Closed-form test: Yes El-Haj-Mahmoud © 2004 CASES 2004

Dynamic Switch on Memory Access: Possibly High Performance but Intractable DEADLINE MISSED Memory overlap: Possible (unfair for low priority) Closed-form test: No Must examine memory positioning! El-Haj-Mahmoud © 2004 CASES 2004

Deterministic Switching: High Performance and Tractable Memory overlap: Yes (fair and bounded) Closed-form test: Yes El-Haj-Mahmoud © 2004 CASES 2004

Tractability through Deterministic Switching Fully decouple independent tasks by forcing periodic switches Every task gets a chance to initiate/overlap memory accesses No scheduling dependences No specificity regarding memory positioning El-Haj-Mahmoud © 2004 CASES 2004

Weighted-Round-Robin (WRR) Round i Round i+1 Round i+2 duty cycle Pipeline T1 T2 T3 T4 T1 T2 T3 T4 T1 T2 T3 T4 time round = memory latency Aggregate computation is the same regardless of context switching Virt. Proc. 1 T1 T1 T1 Virt. Proc. 2 T2 T2 T2 Virt. Proc. 3 T3 T3 T3 Virt. Proc. 4 T4 T4 T4 T4 memory transfer operation forced pre-emption dilate WCET El-Haj-Mahmoud © 2004 CASES 2004

Analytical Framework for WRR d: duty cycle 0 < d  1 P: period = deadline WCET: Worst-Case Execution Time WCET = C + M C: aggregate computation time M: aggregate memory time WCET’: dilated Worst-Case Execution Time WCET’ = (C/d) + M El-Haj-Mahmoud © 2004 CASES 2004

Schedulability Test 1. Dilated task meets deadline on its virtual processor 2. Sum of all duty cycles less than or equal to 1 El-Haj-Mahmoud © 2004 CASES 2004

Generalized Analytical Framework Multiple tasks per VP: El-Haj-Mahmoud © 2004 CASES 2004

Modeling Bus and Memory System Addressed in detail in paper Analysis accounts for: Worst-case task serialization on memory bus DRAM bank conflicts Multiple VPs sharing single DRAM bank El-Haj-Mahmoud © 2004 CASES 2004

Results mem component 28% 50% El-Haj-Mahmoud © 2004 CASES 2004

Novel Memory overlap Formalism (safety & tractability) Classic real-time No Yes Classic multithreading Our real-time multithreading framework El-Haj-Mahmoud © 2004 CASES 2004

Useful Fully capitalize on high-frequency embedded microprocessors Exceed schedulability limit of conventional real-time theory for uniprocessors by analytically bounding WCET overlap El-Haj-Mahmoud © 2004 CASES 2004

Deployable Software-only solution Use Ubicom IP3023 8-thread embedded microprocessor Analytical framework + scheduling policy El-Haj-Mahmoud © 2004 CASES 2004

Summary Safely expose multithreading to hard-real-time schedulability analysis Bound computation / memory overlap Offline closed-form schedulability test Safe Tractable Scale “Memory Wall” in embedded systems Expose full benefits of high-frequency embedded processors El-Haj-Mahmoud © 2004 CASES 2004

Questions? El-Haj-Mahmoud © 2004 CASES 2004