FPGA-Based System Design: Chapter 3 Copyright  2004 Prentice Hall PTR Circuit design for FPGAs n Static CMOS gate vs. LUT n LE output drivers n Interconnect.

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Presentation transcript:

FPGA-Based System Design: Chapter 3 Copyright  2004 Prentice Hall PTR Circuit design for FPGAs n Static CMOS gate vs. LUT n LE output drivers n Interconnect circuits n Clock drivers

FPGA-Based System Design: Chapter 3 Copyright  2004 Prentice Hall PTR Static CMOS gate vs. LUT n Number of transistors: –NAND/NOR gate has 2n transistors. –4-input LUT has 128 transistors in SRAM, 96 in multiplexer. n Delay: –4-input NAND gate has 9  delay. –SRAM decoding has 21  delay. n Power: –Static gate’s power depends on activity. –SRAM always burns power.

FPGA-Based System Design: Chapter 3 Copyright  2004 Prentice Hall PTR LE output drivers n Must drive load –Wire; –Destination LE. n Different types of wiring –present different loads

FPGA-Based System Design: Chapter 3 Copyright  2004 Prentice Hall PTR Interconnect circuits n Why so many types of interconnect? –Provide a choice of delay alternatives. n Sources of delay: –Wires. –Programming points.

FPGA-Based System Design: Chapter 3 Copyright  2004 Prentice Hall PTR Styles of programmable interconnection point pass transistor Three-state

FPGA-Based System Design: Chapter 3 Copyright  2004 Prentice Hall PTR Pass transistor programmable interconnect point n Small area. n Resistive switch. n Delay grows as the square of the number of switches.

FPGA-Based System Design: Chapter 3 Copyright  2004 Prentice Hall PTR Three-state programmable interconnection point n Larger area. n Regenerative driver. +

FPGA-Based System Design: Chapter 3 Copyright  2004 Prentice Hall PTR Clock drivers n Clock driver tree

FPGA-Based System Design: Chapter 3 Copyright  2004 Prentice Hall PTR Clock nets n Must drive all LEs n Design parameters –number of fanouts –load per fanout –wiring tree capacitance n Determine optimal buffer sizes