Lecture 18 OUTLINE The MOS Capacitor (cont’d) – Effect of oxide charges – V T adjustment – Poly-Si gate depletion effect Reading: Pierret ; Hu

Oxide Charges In real MOS devices, there is always some charge within the oxide and at the Si/oxide interface. EE130/230A Fall 2013Lecture 18, Slide 2 Within the oxide: – Trapped charge Q ot High-energy electrons and/or holes injected into oxide – Mobile charge Q M Alkali-metal ions, which have sufficient mobility to drift in oxide under an applied electric field At the interface: – Fixed charge Q F Excess Si (?) – Trapped charge Q IT Dangling bonds R. F. Pierret, Semiconductor Device Fundamentals, Fig. 18.4

Effect of Oxide Charges In general, charges in the oxide cause a shift in the gate voltage required to reach threshold condition: (x is defined to be 0 at metal-oxide interface) For example, positive charge in the oxide near to the p-type Si substrate (for an NMOS device) helps to deplete the surface of holes, so that the gate voltage that must be applied to invert the surface (to become n- type) is reduced, i.e. V T is reduced   V T is negative. In addition, oxide charge can affect the field-effect mobility of mobile carriers (in a MOSFET) due to Coulombic scattering. EE130/230A Fall 2013Lecture 18, Slide 3

Fixed Oxide Charge, Q F EcEc E FS EvEv E c = E FM EvEv MOS 3.1 eV 4.8 eV |qV FB | qQ F / C ox EE130/230A Fall 2013Lecture 18, Slide 4

Parameter Extraction from C-V From a single C-V measurement, we can extract much information about the MOS device: Suppose we know the gate material is heavily doped n-type poly-Si (  M = 4.1 eV), and the gate dielectric is SiO 2 (  r = 3.9): 1.From C max = C ox we can determine oxide thickness x o 2.From C min and C ox we can determine substrate doping (by iteration) 3.From substrate doping and C ox we can find flat-band capacitance C FB 4.From the C-V curve, we can find 5.From  M,  S, C ox, and V FB we can determine Q f EE130/230A Fall 2013Lecture 18, Slide 5

Determination of  M and Q F Measure C-V characteristics of capacitors with different oxide thicknesses. Plot V FB as a function of x o : EE130/230A Fall 2013Lecture 18, Slide 6 C. C. Hu, Modern Semiconductor Devices for Integrated Circuits, Figure 5-21

Mobile Oxide Charge, Q M Na + located at upper SiO 2 interface  no effect on V FB Na + located at lower SiO 2 interface  reduces V FB  V FB Positive oxide charge shifts the flatband voltage in the negative direction: Lecture 19, Slide 7EE130/230A Fall 2013 Bias-Temperature Stress (BTS) Measurement R. F. Pierret, Semiconductor Device Fundamentals, p. 657

Interface Trap Charge, Q IT Traps cause “sloppy” C-V and also greatly degrade mobility in channel “Donor-like” traps are charge-neutral when filled, positively charged when empty Positive oxide charge causes C-V curve to shift toward left. As V G decreases, there is more positive interface charge and hence the “ideal C-V curve” is shifted more to the left. (a) (b) (c) EE130/230A Fall 2013Lecture 18, Slide 8 R. F. Pierret, Semiconductor Device Fundamentals, Fig R. F. Pierret, Semiconductor Device Fundamentals, Fig

V T Adjustment In modern IC fabrication processes, the threshold voltages of MOS transistors are adjusted by adding dopants to the Si by a process called “ion implantation”: – A relatively small dose N I (units: ions/cm 2 ) of dopant atoms is implanted into the near-surface region of the semiconductor – When the MOS device is biased in depletion or inversion, the implanted dopants add to (or substract from) the depletion charge near the oxide-semiconductor interface. EE130/230A Fall 2013Lecture 18, Slide 9

Poly-Si Gate Technology A heavily doped film of polycrystalline silicon (poly-Si) is often employed as the gate-electrode material in MOS devices. – There are practical limits to the electrically active dopant concentration (usually less than 1x10 20 cm -3 )  The gate must be considered as a semiconductor, rather than a metal p-type Si n + poly-Si n-type Si p + poly-Si NMOSPMOS EE130/230A Fall 2013Lecture 18, Slide 10

MOS Band Diagram w/ Gate Depletion How can gate depletion be minimized? V G is effectively reduced: EcEc E FS EvEv EvEv qV G qSqS WTWT p-type Sin+ poly-Si gate EcEc qV poly W poly Si biased to inversion: EE130/230A Fall 2013Lecture 18, Slide 11

Gate Depletion Effect n+ poly-Si Gauss’s Law dictates that W poly =  ox E ox / qN poly x o is effectively increased: p-type Si N C poly C ox EE130/230A Fall 2013Lecture 18, Slide 12

Example: Gate Depletion Effect The voltage across a 2 nm oxide is V ox = 1 V. The active dopant concentration within the n + poly-Si gate is N poly = 8  cm -3 and the Si substrate doping concentration N A is cm -3. Find (a) W poly, (b) V poly, and (c) V T. Solution: (a) W poly =  ox E ox / qN poly =  ox V ox / x o qN poly EE130/230A Fall 2013Lecture 18, Slide 13

(b) (c) EE130/230A Fall 2013Lecture 18, Slide 14

Inversion-Layer Thickness, T inv The average inversion-layer location below the Si/SiO 2 interface is called the inversion-layer thickness, T inv. EE130/230A Fall 2013Lecture 18, Slide 15 C. C. Hu, Modern Semiconductor Devices for Integrated Circuits, Figure 5-24

Effective Oxide Thickness, T oxe (V G + V T )/T oxe can be shown to be the average electric field in the inversion layer. T inv of holes is larger than that of electrons due to difference in effective masses. EE130/230A Fall 2013Lecture 18, Slide 16 C. C. Hu, Modern Semiconductor Devices for Integrated Circuits, Figure 5-25

Effective Oxide Capacitance, C oxe EE130/230A Fall 2013Lecture 18, Slide 17 C. C. Hu, Modern Semiconductor Devices for Integrated Circuits, Figure 5-26