Dominance Fault Collapsing 1 VLSI TESTING PROJECT Dominance Fault Collapsing Anandshankar Mudlapur Arun Balaji Kannan Muthu Balaji Ramkumar Muthu Balan.

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Presentation transcript:

Dominance Fault Collapsing 1 VLSI TESTING PROJECT Dominance Fault Collapsing Anandshankar Mudlapur Arun Balaji Kannan Muthu Balaji Ramkumar Muthu Balan Varadharajaperumal

Dominance Fault Collapsing2 SA0,SA1 SA1 Dominance collapsed faultsUn-collapsed faults Dominance collapsed faults for an AND gate A B A B C C Faults Test Vectors “AB” A-SA011 A-SA101 B-SA011 B-SA110 C-SA011 C-SA1 00, 01, 10 Compulsory Fault Collapsed Faults A-SA0B-SA0,C-SA0 A-SA1C-SA1 B-SA1C-SA1

Dominance Fault Collapsing3 Dominant faults modeled on different gates and fan-outs A A A A A A A A B B B B B A1 A2 A C C C C C C Compulsory Faults Optional Faults A-SA1, B-SA1 A-SA0 or B-SA0 A-SA0, B-SA0 A-SA1 or B-SA1 A-SA1, B-SA1 A-SA0 or B-SA0 A-SA0, B-SA0 A-SA1 or B-SA1 A-SA0, A-SA1 - A-SA0, A-SA1, B-SA0, B-SA1, C-SA0, C-SA1 - A-SA0, A-SA1, A1-SA0, A1-SA1, A2-SA0, A2-SA1 - A-SA0, A-SA1 -

Dominance Fault Collapsing4 Algorithm  Necessary information is read from the bench file  Parse the circuit from input to output or vice-versa  Check if the node is of type XOR and assign the compulsory faults ( SA0 and SA1) at the output. Repeat for all nodes:  Check if node is an input and if fan-outs are greater than 2 assign both faults for the node.  All the inputs of the gates are scanned and checked for the node type o If fan-out of the input >= 2, assign compulsory fault o Else if gate is BUF or NOT and input is PI assign both faults o Else if PI, assign compulsory fault and note input # o Else if gate output, set a FLAG

Dominance Fault Collapsing5  Check if FLAG is unchanged and if no primary inputs are encountered; assign the optional fault to the last input  Else if FLAG is unchanged; assign the optional fault to the PI End Loop  If PO has fan-outs; both faults are assigned  The result obtained is saved! Algorithm Continued…

Dominance Fault Collapsing A D C G F B E H K J L M Example of Dominance Fault collapsing using the above algorithm 6

Dominance Fault Collapsing 0,1 A D C G F B E H K J L M Example of Dominance Fault collapsing using the above algorithm 6

Dominance Fault Collapsing 0,1 A D C G F B E H K J L M Example of Dominance Fault collapsing using the above algorithm 0,1 6

Dominance Fault Collapsing 0,1 A D C G F B E H K J L M Example of Dominance Fault collapsing using the above algorithm 0,1 1 6

Dominance Fault Collapsing 0,1 A D C G F B E H K J L M Example of Dominance Fault collapsing using the above algorithm 0,

Dominance Fault Collapsing 0,1 A D C G F B E H K J L M Example of Dominance Fault collapsing using the above algorithm 0,

Dominance Fault Collapsing 0,1 A D C G F B E H K J L M Example of Dominance Fault collapsing using the above algorithm 0,

Dominance Fault Collapsing 0,1 A D C G F B E H K J L M Example of Dominance Fault collapsing using the above algorithm 0,

Dominance Fault Collapsing 0,1 A D C G F B E H K J L M Example of Dominance Fault collapsing using the above algorithm 0,

Dominance Fault Collapsing 0,1 A D C G F B E H K J L M Example of Dominance Fault collapsing using the above algorithm 0,

Dominance Fault Collapsing 0,1 A D C G F B E H K J L M Example of Dominance Fault collapsing using the above algorithm 0,

Dominance Fault Collapsing 0,1 A D C G F B E H K J L M Example of Dominance Fault collapsing using the above algorithm 0,

Dominance Fault Collapsing 0,1 A D C G F B E H K J L M Example of Dominance Fault collapsing using the above algorithm 0,

Dominance Fault Collapsing Results Benchmark Circuits C Total Faults (HITEC GENERATED) CollapsingMethodEquivalenceDominance Benchmark circuit HITEC Our Program C (XOR) (NAND MODEL for XOR)

Dominance Fault Collapsing Conclusion As a conclusion,  Results may coincidentally match!  A Double check on the results : always advisable  Plan what you do, do what you plan and record what you have accomplished! 8