COARSE GRAINED RECONFIGURABLE ARCHITECTURES 04/18/2014 Aditi Sharma Dhiraj Chaudhary Pruthvi Gowda Rachana Raj Sunku DAY - 1 1

Outline Introduction Motivation Architectures MATRIX RaPiD RAW CHESS DReAM 2

Reconfigurable architecture Fine GrainedCoarse Grained ????? 3

Reconfigurable Architectures Fine Grained Architecture Coarse Grained Architecture 4

Processing Elements Fine Grained Reconfigurable Architecture (FPGA) Coarse Grained Reconfigurable Architecture 5

Motivation Disadvantages of Fine Grained Architecture? Large routing area (80% of chip area) Large volume of configuration data Low area efficiency for arithmetic operations Reduced clock speed and bandwidth Advantages of Coarse Grained Architecture? Lesser number of PE’s so Placement and Routing problem is less complex and is much faster Lesser area of chip devoted to routing and configuration context. Low power consumption Fast reconfiguration 6

Coarse Grained Architectures MATRIX RaPiD RAW CHESS DReAM 7

MATRIX- Multiple Alu archiTecture with Reconfigurable Interconnect eXperiment Developed at MIT by Andre DeHon in Designed for general purpose applications. Then why not use general purpose processor?? 8

What is reconfigurable in MATRIX? Instruction Stores Control Elements Data Stores Interconnections What else you need?? 9

MATRIX - Basic Functional Unit (BFU) 10 Mirsky, E., & DeHon, A. (1996, April). MATRIX: a reconfigurable computing architecture with configurable instruction distribution and deployable resources. In FPGAs for Custom Computing Machines, Proceedings. IEEE Symposium on (pp ). IEEE.

MATRIX - Interconnection Network 11 Mirsky, E., & DeHon, A. (1996, April). MATRIX: a reconfigurable computing architecture with configurable instruction distribution and deployable resources. In FPGAs for Custom Computing Machines, Proceedings. IEEE Symposium on (pp ). IEEE.

MATRIX - Switch/Port Architecture Different modes of MATRIX port: Static Value mode Static Source mode Dynamic Source mode 12 Mirsky, E., & DeHon, A. (1996, April). MATRIX: a reconfigurable computing architecture with configurable instruction distribution and deployable resources. In FPGAs for Custom Computing Machines, Proceedings. IEEE Symposium on (pp ). IEEE.

MATRIX Application Example: FIR Sample values are passed through first row Produces results every 2 clock cycles Needs 4K cells to implement Area Comparison: MATRIX takes 58Mλ2 FPGA takes up to125Mλ2 for decent performance. 13 Mirsky, E., & DeHon, A. (1996, April). MATRIX: a reconfigurable computing architecture with configurable instruction distribution and deployable resources. In FPGAs for Custom Computing Machines, Proceedings. IEEE Symposium on (pp ). IEEE.

RaPiD - Introduction ReconfigurAble PIpelined Datapath Designed at University of Washington in 1996 Coarse grained field programmable architecture for constructing deep computational pipelines Optimized for highly repetitive, computation-intensive tasks Motivation Compile regular computations into an application specific datapath and the program for controlling that datapath Configurable computing performance - close to ASIC Flexibility – close to General Purpose Processor Suitable for DSP Applications 14

RaPiD - Emulator 15 Fisher, Chris, et al. "An emulator for exploring RaPiD configurable computing architectures.“Field- Programmable Logic and Applications. Springer Berlin Heidelberg, 2001.

RaPiD – Block Diagram RaPiD Architecture Block Diagram 16 Cronquist, Darren C., et al. "Architecture design of reconfigurable pipelined datapaths.“Advanced Research in VLSI, Proceedings. 20th Anniversary Conference on. IEEE, 1999.

RaPiD – Basic Cell The Basic Cell of RaPiD-1 17 Cronquist, Darren C., et al. "Architecture design of reconfigurable pipelined datapaths.“Advanced Research in VLSI, Proceedings. 20th Anniversary Conference on. IEEE, 1999.

RaPiD – Functional Unit Generic Functional Unit Configurable Delay 18 Cronquist, Darren C., et al. "Architecture design of reconfigurable pipelined datapaths.“Advanced Research in VLSI, Proceedings. 20th Anniversary Conference on. IEEE, 1999.

RaPiD – Interconnect Interconnect Between FU and Buses Bus Connector Ebeling, Carl, Darren C. Cronquist, and Paul Franklin. "RaPiD—Reconfigurable pipelined datapath.“ 2. Cronquist, Darren C., et al. "Architecture design of reconfigurable pipelined datapaths."

RaPiD – Local Memory Local Memory 20 Ebeling, Carl, Darren C. Cronquist, and Paul Franklin. "RaPiD—Reconfigurable pipelined datapath.“Field- Programmable Logic Smart Applications, New Paradigms and Compilers. Springer Berlin Heidelberg, 1996.

RaPiD Application Example: FIR 21 Algorithm for FIR Filter Ebeling, Carl, et al. "Mapping applications to the RaPiD configurable architecture." Field-Programmable Custom Computing Machines, Proceedings., The 5th Annual IEEE Symposium on. IEEE, 1997.

RaPiD Application Example: FIR 22 One cell of the FIR Filter Ebeling, Carl, et al. "Mapping applications to the RaPiD configurable architecture." Field-Programmable Custom Computing Machines, Proceedings., The 5th Annual IEEE Symposium on. IEEE, 1997.

RaPiD – Performance High performance for computationally intensive tasks RaPiD is low-powered Local Communication, distributed memories, clock disabling It can be a closely coupled co-processor 23 Cronquist, Darren C., et al. "Architecture design of reconfigurable pipelined datapaths.“Advanced Research in VLSI, Proceedings. 20th Anniversary Conference on. IEEE, 1999.

RaPiD – Issues Not suited for tasks that are unstructured not highly repetitive control flow strongly depends on the data Underutilization of Resources It is not clear how RaPiD can be coupled to a generic RISC processor 24