Project SRAM Stevo Bailey Kevin Linger Roger Lorenzo John Thompson ECE 4332: Intro to VLSI

PICo’s Projects 1.1 Mb low-power SRAM – (E a ) 2 (t p )(A)(P idle ) 2.64 kb high-speed cache – (E a )(t p ) 2 (A)(P idle ) ECE 4332: Intro to VLSI

Problem Description 1 Mb SRAM 32-bit words Inputs: address, input word, read, write, clock Outputs: output word Robust across process, voltage, and temp Special features optional Minimize power ECE 4332: Intro to VLSI

Claim ECE 4332: Intro to VLSI We designed and simulated a competitive 1 Mb SRAM. 1.SRAM Architecture 2.Bitcell Optimizations 3.SRAM Model Simulations 4.Layout Optimizations 5.Results and Further Work

SRAM Block Diagram [final block diagram] ECE 4332: Intro to VLSI

Claim ECE 4332: Intro to VLSI 1.SRAM Architecture 2.Bitcell Optimizations 3.SRAM Model Simulations 4.Layout Optimizations 5.Results and Further Work

Bitcell 6T-bitcell – µm 2 ECE 4332: Intro to VLSI 2x2 bitcell array

Bitcell ECE 4332: Intro to VLSI

Bitcell ECE 4332: Intro to VLSI

Bitcell [SNM monte carlo] ECE 4332: Intro to VLSI

Claim ECE 4332: Intro to VLSI 1.SRAM Architecture 2.Bitcell Optimizations 3.SRAM Model Simulations 4.Layout Optimizations 5.Results and Further Work

SRAM Model ECE 4332: Intro to VLSI

SRAM Model ECE 4332: Intro to VLSI C values obtained from parasitic extraction R values from NCSU wiki on FreePDK45 (

SRAM Model ECE 4332: Intro to VLSI

SRAM Model Example decoder with predecoding stage [We omitted this figure because of copyright laws. The image is in the Rabaey book and available online. If you really, really need to see it, go to download the power point slides for chapter 12, and go to slide 57.]

ECE 4332: Intro to VLSI SRAM Model

SRAM Model Results ECE 4332: Intro to VLSI

SRAM Model Results ECE 4332: Intro to VLSI 256 Rows, 64 Columns, 64 Blocks

ECE 4332: Intro to VLSI Timing Diagram

Claim ECE 4332: Intro to VLSI 1.SRAM Architecture 2.Bitcell Optimizations 3.SRAM Model Simulations 4.Layout Optimizations 5.Results and Further Work

ECE 4332: Intro to VLSI Layouts Address Decoders Write/Sense Amps Block DeMux Write/Sense Amps Block DeMux 256 by 64 Block

ECE 4332: Intro to VLSI Layouts 2x2 Bit Cells 2x Read/Write Mux Sense Amp WL[0] WL[1] BL[0]BLB[0] BL[1] BLB[1] VDDGNDVDDGND SA[0] SAB[0]SA[1]SAB[1] WAB[1]WA[1]WAB[0]WA[0] Enable SAOB[1] SAO[1] SAOB[0] SAO[0]

Claim ECE 4332: Intro to VLSI 1.SRAM Architecture 2.Bitcell Optimizations 3.SRAM Model Simulations 4.Layout Optimizations 5.Results and Further Work

ECE 4332: Intro to VLSI Results verified functionality at all process corners (TT, FF, FS, SF, SS) VDD = { 0.54, 0.60, 0.66, 1.0, 1.1, 1.2 } volts temp = { 0°, 27°, 54° } Celsius SS forced a longer clock period for a read

ECE 4332: Intro to VLSI Metrics Total Energy1.46 pJ Read Energy1.43 pJ Write Energy1.57 pJ Read Delay2.9 ns Write Delay1.97 ns Total Delay2.9 ns Idle Power208 µW Sleep Power99.2 µW Bitcell Area0.819 µm 2 Total Area1.04 mm 2 Final Metric1.337x J 2 ·s·mm 2 ·W

ECE 4332: Intro to VLSI Error Correcting Code SEC-DED

ECE 4332: Intro to VLSI Sources B. Jacob, S. W. Ng, and D. T. Wang, Memory systems: Cache, DRAM, disk, Burlington, MA: Morgan Kaufmann, 2008, p B. S. Amrutur and M. A. Horowitz, “Fast low-power decoders for RAMs,” JSSC, vol. 36, no. 10, J. F. Ryan and B. H. Calhoun, “Minimizing offset for latching voltage-mode sense amplifiers for sub-threshold operation,” ISQED, J. Rabaey, A. Chandrakasan, and B. Nikolic, Digital integrated circuits, 2nd ed., Upper Saddle River: Pearson, 2003, p J. Yeung and H. Mahmoodi, "Robust sense amplifier design under random dopant fluctuations in nano-scale CMOS technologies," SOC Conference, 2006 IEEE International, 2006, pp L. Hamouche and B. Allard, “Low power options for 32nm always-on SRAM architecture,” Solid State Electronics, 2011.

ECE 4332: Intro to VLSI Acknowledgements Benton Calhoun, PICo liason Team XOR (2010) Dominic Carr Jae Park Daniel Reyno Team 2 (2010) Yanran Chen Cary Converse Chenqian Gan David Moore

Questions? ECE 4332: Intro to VLSI