Session 5: Projects 1. Physical Limits of Technology Scaling : 2 SCALING AND EFFICIENCY.

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Presentation transcript:

Session 5: Projects 1

Physical Limits of Technology Scaling : 2 SCALING AND EFFICIENCY

RLC extraction : 3 Inductance Modeling Reducing Capacitance Skin Effect / Anomalous Skin Effect

Interconnect Delay : 4 High Speed Global On-Chip Interconnects Compact Model for Delay Near Speed-of-Light On-Chip Electrical Interconnects Moment-Matching Technique

Interconnect Noise : 5 Moment-Matching Technique

Repeater Insertion: 6

Bit Rate Limitation : 7 Data Integrity : maximum data transfer rate. Digital communication Throughput-Centric Wave-Pipelined Interconnect

Process Variations : 8

Power Dissipation : 9

Clock Distribution : 10

3D Integration: 11 Electrical modeling of Interconnects in 3-D ICs

Speed/Power/Area Tradeoffs : 12

Power Distribution / Electromigration : 13 Design / Analysis / Optimization of power distribution network Local power distribution network Global power distribution network

Impact of Cu vs. Al Metallization on Performance : 14

Thermal Modeling of Metallic Interconnects : 15

CNTs as Interconnect: 16 PERFORMANCE COMPARISON BETWEEN COPPER, CARBON NANOTUBE, AND OPTICS FOR OFF-CHIP AND ON-CHIP INTERCONNECTS

Optical Interconnects : 17