Ben Gaudette Michael Pfeister CSE 520 Spring 2010

Project Description Background Stream Processing is a paradigm that exploits parallel processing via data parallelism Stream Processors include GPU’s, PPU’s, Cell Processor (with software support), and the Imagine/Storm-1. Project Goal Create a simulator for a Stream Processor based on the Imagine.

Imagine Processor - History Originally an academic based project. Lead by William Dally of Stanford Created Isim Students took all of the deliverables away and created a start up company: SPI

Imagine Processor - Resources The VLSI Implementation and Evaluation of Area- and Energy-Efficient Streaming Media Processors by Brucek Khailany _onesided.pdf _onesided.pdf Imagine Programming System User’s Guide by Peter Mattson. Imagine Home Page

Imagine Processor - Architecture

Imagine Processor – ALU Cluster 3 ADD units, 2 MUL, 1 DSQ, 1 SP, 1 COMM Each input has a 16 word Local Register File An Intracluster Switch is used to connect all FU outputs to all LRF’s.

Imagine Processor – “our” ALU Cluster 3 ADD units, 2 MUL, 1 DSQ Each FU has a 32 word Local Register File A perfect Intracluster Switch is used to connect all FU ouputs to all LRF’s.

Imagine Processor – ADD FU ADD unit is fully pipelined to 4 stages Instructions: FADD/FSUB – 4 cycles ADD/SUB – 2 cycles ILT/ILEFLT/FLE – 2 cycles IEQ/NEQ – 1 cycle AND/OR/XOR/NOT – 1 cycle FTOI – 3 cycles ITOF – 4 cycles

Imagine Processor – MUL FU MUL unit is fully pipelined to 4 stages Instructions: FMUL – 4 cycles IMUL – 4 cycles UMUL – 4 cycles

Imagine Processor – DSQ FU DSQ unit is not pipelined Instructions: FDIV – 17 cycles FSQRT – 16 cycles IDIV/UDIV – 22 cycles IDIVR/UDIVR – 23 cycles

Imagine Processor – SP & COMM FU SP unit 256 Word Scratchpad One Read Port One Write Port COMM unit Exchanges data between clusters when a stream is not completely data parallel.

Imagine Processor – SRF

Imagine Processor – Microcontroller