Inverter Chapter 5 The Inverter April 10, 2003

Inverter Objective of This Chapter  Use Inverter to know basic CMOS Circuits Operations  Watch for performance Index such as  Speed (Delay calculation)  Optimal Transistor Sizing for speed and Energy  Power Consumption and Dissipation

Inverter The CMOS Inverter: A First Glance V in V out C L V DD

Inverter CMOS Inverter Polysilicon In Out V DD GND PMOS Metal 1 NMOS Contacts N Well

Inverter Two Inverters Connect in Metal Share power and ground Abut cells Vin Vout Vin Vout

Inverter CMOS Inverter First-Order DC Analysis V OL = 0 V OH = V DD V DD V V in = V DD V in = 0 V out V R n R p

Inverter Delay Definitions

Inverter CMOS Inverter: Transient Response t pHL = f(R on.C.C L ) = 0.69 R on C L V out V R n R p V DD V V in = V DD V in = 0 (a) Low-to-high(b) High-to-low C L C L ln(2)=0.69

Inverter Voltage Transfer Characteristic

Inverter PMOS Load Lines V DS,p I Dp V GSp =-2.5 V GSp =-1 V DS,p I Dn V in =0 V in =1.5 V out I Dn V in =0 V in =1.5 V in = V DD +V+V GSp I Dn = - I Dp V out = V DD +V+V DSp V out I Dn V in = V DD +V+V GS,p I D,n = - I D,p V out = V DD +V+V DS,p (Vdd = 2.5V in 0.25um CMOS Process) (Vt = 0.4V as shown in Table 3-2)

Inverter CMOS Inverter Load Characteristics

Inverter CMOS Inverter VTC V M: Vin = Vout Switching Threshold Voltage

Inverter Switching Threshold as a Function of Transistor Ratio NMOS and PMOS are in Saturation Modes For r = 1, and saturated velocity NMOS = 2 PMOS, Wp = 2Wn

Inverter Switching Threshold as a Function of Transistor Ratio M V (V) W p /W/W n

Inverter Simulated VTC

Inverter Impact of Process Variations V in (V) V out (V) Good PMOS Bad NMOS Good NMOS Bad PMOS Nominal Good: Smaller oxide thickness, smaller L, higher W, smaller VT

Inverter Propagation Delay

Inverter CMOS Inverters Polysilicon In Out Metal1 V DD GND PMOS NMOS 1.2  m =2

Inverter CMOS Inverter Propagation Delay

Inverter The Transistor as a Switch

Inverter The Transistor as a Switch

Inverter The Transistor as a Switch

Inverter Transient Response t p = 0.69 C L (R eqn +R eqp )/2 ? t pLH t pHL

Inverter Design for Performance  Keep loading capacitances (C L ) small  Increase transistor sizes (add CMOS gain)  Watch out for self-loading (for the previous stage)!  Increase V DD (????)  Power consumption??

Inverter Delay (speed degrade) as a function of V DD

Inverter NMOS/PMOS ratio tpLH tpHL tp  = W p /W n (See pp. 204) Fig. 5-18

Inverter Device Sizing (for fixed load) Self-loading effect: Intrinsic capacitances dominate (Fig. 5-19)

Inverter Inverter Sizing

Inverter Inverter Chain CLCL If C L is given: - How many stages are needed to minimize the delay? - How to size the inverters? May need some additional constraints. In Out 1f2f1

Inverter Inverter Delay Minimum length devices, L=0.25  m Assume that for W P = 2W N =2W same pull-up and pull-down currents approx. equal resistances R N = R P approx. equal rise t pLH and fall t pHL delays Analyze as an RC network t pHL = (ln 2) R N C L t pLH = (ln 2) R P C L Delay (D): 2W2W W Load for the next stage:

Inverter Inverter with Load Load (C L ) Delay Assumptions: no load  zero delay CLCL t p = k R W C L RWRW RWRW W unit = 1 k is a constant, equal to 0.69

Inverter Inverter with Load and Para. Cap. Load Delay C int CLCL Delay = kR W (C int + C L ) = kR W C int + kR W C L = kR W C int (1+ C L /C int ) = Delay (Internal) + Delay (Load) C N = C unit C P = 2C unit 2W2W W

Inverter Delay Formula C int =  C gin with   1 f = C L /C gin - effective fanout R = R unit /W ; C int =WC unit t p0 = 0.69R unit C unit

Inverter Apply to Inverter Chain CLCL InOut 12N t p = t p1 + t p2 + …+ t pN

Inverter Optimal Tapering for Given N Delay equation has (N-1) unknowns, C gin,2 – C gin,N Minimize the delay, find N - 1 partial derivatives Result: C gin,j+1 /C gin,j = C gin,j /C gin,j-1 Size of each stage is the geometric mean of two neighbors - Each stage has the same effective fanout (C out /C in ) - Each stage has the same delay

Inverter Optimum Delay and Number of Stages When each stage is sized by f and has same effective fanout f: Minimum path delay Effective fanout of each stage:

Inverter Example C L = 8 C 1 In Out C1C1 1ff2f2 C L /C 1 has to be evenly distributed across N = 3 stages:

Inverter Optimum Number of Stages For a given load, C L and given input capacitance C in Find optimal sizing f For  = 0, f = e, N = lnF

Inverter Optimum Effective Fanout f Optimum f for given process defined by  f opt = 3.6 for  =1

Inverter Impact of Self-Loading on tp No Self-Loading,  =0 With Self-Loading  =1

Inverter Normalized delay function of F

Inverter Buffer Design Nft p

Inverter Power Dissipation

Inverter Where Does Power Go in CMOS?

Inverter Dynamic Power Dissipation Energy/transition = C L * V dd 2 Power = Energy/transition *f =C L * V dd 2 * f Need to reduce C L, V dd, andf to reduce power. VinVout C L Vdd Not a function of transistor sizes!

Inverter Modification for Circuits with Reduced Swing

Inverter Node Transition Activity and Power

Inverter Transistor Sizing for Minimum Energy  Goal: Minimize Energy of whole circuit  Design parameters: f and V DD  tp  tpref of circuit with f=1 and V DD =V ref

Inverter Transistor Sizing (2)  Performance Constraint (  =1)  Energy for single Transition

Inverter Transistor Sizing (3) F = V DD = f (f) E/E ref = f (f)

Inverter Short Circuit Currents

Inverter How to keep Short-Circuit Currents Low? Short circuit current goes to zero if t fall >> t rise, but can’t do this for cascade logic, so...

Inverter Minimizing Short-Circuit Power Vdd =1.5 Vdd =2.5 Vdd =3.3

Inverter Leakage Sub-threshold current one of most compelling issues in low-energy circuit design!

Inverter Reverse-Biased Diode Leakage JS = pA/  m2 at 25 deg C for 0.25  m CMOS JS doubles for every 9 deg C!

Inverter Subthreshold Leakage Component

Inverter Static Power Consumption Wasted energy … Should be avoided in almost all cases, but could help reducing energy in others (e.g. sense amps)

Inverter Principles for Power Reduction  Prime choice: Reduce voltage!  Recent years have seen an acceleration in supply voltage reduction  Design at very low voltages still open question (0.6 … 0.9 V by 2010!)  Reduce switching activity  Reduce physical capacitance  Device Sizing: for F=20 –f opt (energy)=3.53, f opt (performance)=4.47