 Seattle Pacific University EE 1210 - Logic System DesignNMOS-CMOS-1 Voltage-controlled Switches In order to build circuits that implement logic, we need.

Slides:

Advertisements

Similar presentations

Chapter 2 Modern CMOS technology

Advertisements

CSET 4650 Field Programmable Logic Devices

COMP541 Transistors and all that… a brief overview

Lecture 0: Introduction

Kevin Walsh CS 3410, Spring 2010 Computer Science Cornell University Gates and Logic See: P&H Appendix C.2, C.3 xkcd.com/74/

EE42/100, Spring 2006Week 14a, Prof. White1 Week 14a Propagation delay of logic gates CMOS (complementary MOS) logic gates Pull-down and pull-up The basic.

ECE C03 Lecture 41 Lecture 4 Combinational Logic Implementation Technologies Prith Banerjee ECE C03 Advanced Digital Design Spring 1998.

Lecture #26 Gate delays, MOS logic

EE 4271 VLSI Design, Fall 2011 CMOS Combinational Gate.

Spring 2007EE130 Lecture 35, Slide 1 Lecture #35 OUTLINE The MOS Capacitor: Final comments The MOSFET: Structure and operation Reading: Chapter 17.1.

10/8/2004EE 42 fall 2004 lecture 171 Lecture #17 MOS transistors MIDTERM coming up a week from Monday (October 18 th ) Next Week: Review, examples, circuits.

CSCE 612: VLSI System Design Instructor: Jason D. Bakos.

Copyright 2001, Regents of University of California Lecture 18: 04/0703 A.R. Neureuther Version Date 04/03/03 EECS 42 Intro. electronics for CS Spring.

11/5/2004EE 42 fall 2004 lecture 281 Lecture #28 PMOS LAST TIME: NMOS Electrical Model – NMOS physical structure: W and L and d ox, TODAY: PMOS –Physical.

Introduction to CMOS VLSI Design Lecture 0: Introduction

Computer Engineering 222. VLSI Digital System Design Introduction.

Lecture 21 Today we will Revisit the CMOS inverter, concentrating on logic 0 and logic 1 inputs Come up with an easy model for MOS transistors involved.

Lecture #24 Gates to circuits

Design and Implementation of VLSI Systems (EN0160) Sherief Reda Division of Engineering, Brown University Spring 2007.

(N-Channel Metal Oxide Semiconductor)

11/3/2004EE 42 fall 2004 lecture 271 Lecture #27 MOS LAST TIME: NMOS Electrical Model – Describing the I-V Characteristics – Evaluating the effective resistance.

Lecture #25 Timing issues

Design and Implementation of VLSI Systems (EN1600) lecture02 Sherief Reda Division of Engineering, Brown University Spring 2008 [sources: Weste/Addison.

Computer ArchitectureFall 2008 © August 20 th, Introduction to Computer Architecture Lecture 2 – Digital Logic Design.

ECEN 248: INTRODUCTION TO DIGITAL SYSTEMS DESIGN Lecture 5 Dr. Shi Dept. of Electrical and Computer Engineering.

10-7 Metal-Oxide Semiconductor （ MOS ）  Field-Effect Transistor （ FET ） Unipolar transistor Depend on the flow of only one type of carrier JFET, MOS 

12/10/2004EE 42 fall 2004 lecture 421 Lecture #42: Transistors, digital This week we will be reviewing the material learned during the course Today: review.

S. RossEECS 40 Spring 2003 Lecture 24 Today we will Review charging of output capacitance (origin of gate delay) Calculate output capacitance Discuss fan-out.

Lecture 0: Introduction. CMOS VLSI Design 4th Ed. 0: Introduction2 Introduction  Integrated circuits: many transistors on one chip.  Very Large Scale.

Introduction Integrated circuits: many transistors on one chip.

CSET 4650 Field Programmable Logic Devices

Lecture 19 OUTLINE The MOSFET: Structure and operation

ECE 331 – Digital System Design Transistor Technologies, and Realizing Logic Gates using CMOS Circuits (Lecture #23)

Transistors Three-terminal devices with three doped silicon regions and two P-N junctions versus a diode with two doped regions and one P-N junction Two.

Z. Feng VLSI Design 1.1 VLSI Design MOSFET Zhuo Feng.

1 Delay Estimation Most digital designs have multiple data paths some of which are not critical. The critical path is defined as the path the offers the.

EE 5900 Advanced Algorithms for Robust VLSI CAD, Spring 2009

MOS Transistors The gate material of Metal Oxide Semiconductor Field Effect Transistors was original made of metal hence the name. Present day devices’

Chapter 3 Digital Logic Structures. 3-2 Transistor: Building Block of Computers Microprocessors contain millions of transistors Intel Pentium 4 (2000):

Lecture 2 1 Computer Elements Transistors (computing) –How can they be connected to do something useful? –How do we evaluate how fast a logic block is?

Lecture 2. Logic Gates Prof. Taeweon Suh Computer Science Education Korea University 2010 R&E Computer System Education & Research.

Lecture 0: Introduction. CMOS VLSI Design 4th Ed. 0: Introduction2 Introduction  Integrated circuits: many transistors on one chip.  Very Large Scale.

Qualitative Discussion of MOS Transistors. Big Picture ES230 – Diodes – BJT – Op-Amps ES330 – Applications of Op-Amps – CMOS Analog applications Digital.

Class 02 DICCD Transistors: Silicon Transistors are built out of silicon, a semiconductor Pure silicon is a poor conductor (no free charges) Doped.

4-1 Introduction Chapter # 4: Programmable and Steering Logic.

ECE2030 Introduction to Computer Engineering Lecture 4: CMOS Network Prof. Hsien-Hsin Sean Lee School of Electrical and Computer Engineering Georgia Tech.

IEEE’s Hands on Practical Electronics (HOPE) Lesson 8: Transistors.

Computer Organization and Design Transistors and all that… a brief overview Montek Singh Oct 12, 2015 Lecture 9 1.

EE210 Digital Electronics Class Lecture 7 May 22, 2008.

ISAT 436 Micro-/Nanofabrication and Applications Transistors David J. Lawrence Spring 2004.

Introduction to MOS Transistors Section Selected Figures in Chapter 15.

Contemporary Logic Design Prog. & Steering Logic © R.H. Katz Transparency No. 8-1 Chapter # 4: Programmable and Steering Logic Section 4.2.

Terminal Impedances Eq Eq Eq

1 Contents Reviewed Rabaey CH 3, 4, and 6. 2 Physical Structure of MOS Transistors: the NMOS [Adapted from Principles of CMOS VLSI Design by Weste & Eshraghian]

 Seattle Pacific University EE Logic System DesignSwitchLogic-1 Switches AB A simple on/off switch IF switch is closed THEN light is on + 5V -

EECS 270: Inside Logic Gates (CMOS)

Solid-State Devices & Circuits

CMOS Logic Gates. NMOS transistor acts as a switch 2 When gate voltage is 0 V No channel is formed current does not flow easily “open switch” When gate.

Introduction to CMOS Transistor and Transistor Fundamental

CMOS FABRICATION.

Penn ESE370 Fall DeHon 1 ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 4: September 14, 2011 Gates from Transistors.

Electrical Characteristics of Logic Gates Gate Characteristics Last Mod: January 2008  Paul R. Godin.

1 ECE2030 Introduction to Computer Engineering Lecture 4: CMOS Network Prof. Hsien-Hsin Sean Lee School of ECE Georgia Institute of Technology.

University of Texas at Austin CS310 - Computer Organization Spring 2009 Don Fussell CMOS Transistors and Gates.

2007/11/20 Paul C.-P. Chao Optoelectronic System and Control Lab., EE, NCTU P1 Copyright 2015 by Paul Chao, NCTU VLSI Lecture 0: Introduction Paul C.–P.

Computer Organization and Design Transistors and all that… a brief overview Montek Singh Mar 21, 2016 Lecture 9 1.

Introduction to CMOS VLSI Design Lecture 0: Introduction.

COMP541 Transistors and all that… a brief overview

COMP541 Transistors and all that… a brief overview

COMP541 Transistors and all that… a brief overview

Presentation transcript:

 Seattle Pacific University EE Logic System DesignNMOS-CMOS-1 Voltage-controlled Switches In order to build circuits that implement logic, we need voltage-controlled switches Control input = 1  Switch is closed Control input = 0  Switch is open AB Control This can be accomplished with electro-mechanical relays Large, clunky, power-hungry Transistors are a better way Tiny, efficient, fast Source Drain Gate

 Seattle Pacific University EE Logic System DesignNMOS-CMOS-2 Silicon Bulk (p-type) e-e- e-e- e-e- e-e- e-e- e-e- e-e- e-e- e-e MOS Semiconductor Transistors e-e- e-e- e-e- e-e- e-e- Source e-e- e-e- e-e- e-e- Drain Gate n-type Si Source Wire Drain Wire Gate Wire Oxide P-type silicon: Excess positive charges (electron holes) N-type silicon: Excess negative charges (electrons) Oxide: Insulator Gate: Metal pad In this state, current (electrons) cannot flow between source and drain – switch is OPEN

 Seattle Pacific University EE Logic System DesignNMOS-CMOS-3 Silicon Bulk (p-type) MOS Semiconductor Transistors e-e- e-e- e-e- e-e- e-e- Source e-e- e-e- e-e- e-e- Drain Gate n-type Si Source Wire Drain Wire Gate Wire Oxide Place a positive charge on the gate wire (gate = +5V) +5V The gate’s positive charge attracts negatively-charged electrons + e-e- e-e- e-e- e-e- e-e- e-e- e-e- e-e- e-e- This row of electrons forms a channel connecting the Source and Drain – Current can flow – Switch is CLOSED e-e- e-e-

 Seattle Pacific University EE Logic System DesignNMOS-CMOS-4 Voltage-controlled switches Logic 1 on gate: Source and Drain connected Gate Source Drain nMOS Transistor Gate Source Drain pMOS Transistor Logic 0 on gate: Source and Drain connected Gate Source Drain Gate Source Drain nMOS: Good connector to GND Poor connector to +5 pMOS: Poor connector to GND Good connector to +5

 Seattle Pacific University EE Logic System DesignNMOS-CMOS-5 An nMOS Inverter Issues When transistor (switch) is closed, some current goes directly from 5V to GND Wastes power; creates heat 5V GND = 0V V in V out 5V GND = 0V V in V out Replace the switch with an NMOS transistor When transistor (switch) is open, current must flow through the resistor Wastes power; creates heat

 Seattle Pacific University EE Logic System DesignNMOS-CMOS-6 CMOS Inverter Input is 1 Pull-up does not conduct Pull-down conducts Output connected to GND Input is 0 Pull-up conducts Pull-down does not conduct Output connected to Vdd 5V = 1 GND = 0 Pull-up pMOS transistor Pull-down nMOS transistor Current Note that there is never current leakage… GND +5V A Z GND +5V A Z GND +5V A Z 1 0

 Seattle Pacific University EE Logic System DesignNMOS-CMOS-7 CMOS NAND Gate A = 1, B = 1 Output is GND=0 A = 0, B = 1 or A=1, B=0 Output is Vdd=1 Pull-up pMOS Network Pull-down nMOS Network Current 5V=1 GND=0 GND +5V A B Z A = 0, B = 0 Output is Vdd=1 0 0 Current GND +5V A B Z GND +5V A B Z GND +5V A B Z

 Seattle Pacific University EE Logic System DesignNMOS-CMOS-8 CMOS AND Gate Pull-down pMOS Network Pull-up nMOS Network Build an AND gate by mirroring a NAND gate. Problem: nMOS is poor at transmitting 5V and pMOS is poor at transmitting GND Pull-up pMOS Network Pull-down nMOS Network GND +5V A B GND +5V Z Take a NAND gate… and invert the output Takes two more transistors, but works! This is the reason that NANDs/NORs are faster than ANDs/ORs GND A B Z +5V