ENGG3190 Logic Synthesis High Level Synthesis Winter 2014 S. Areibi School of Engineering University of Guelph

Outline Synthesis & Abstraction Levels of DesignSynthesis & Abstraction Levels of Design High Level SynthesisHigh Level Synthesis –Definition –Motivation Main Preprocessing StepsMain Preprocessing Steps –Parsing & Analysis –Optimization –Intermediate Forms (DFG/CFG) Main Processing StepsMain Processing Steps –Allocation –Scheduling –Binding 2

Synthesis of Digital Circuits ComputationalBooleanAlgebra Two Level & Multi Level Logic Synthesis Sequential Logic Synthesis Data Structures PCN BDD’s & SAT Algorithms Logic Synthesis High Level Synthesis RTL NETLIST (Gates & Wires) Physical Synthesis

Abstraction levels System High-level Logic Physical Synthesis step LevelBehaviorStructure

High-Level Synthesis High-level Code Custom Circuit High-Level Synthesis Could be C, C++, Java, Perl, Python, SystemC, ImpulseC, VHDL, Verilog, etc. Usually a RT VHDL description, but could as low level as a bit file

High-Level Synthesis acc = 0; for (i=0; i < 128; i++) acc += a[i]; acc i < addr a[i] x &a In from memory Memory address acc Done Memory Read Controller

High Level Synthesis Constraints Area Time: Clock Period Nr. of clock steps Power +- *< Library WHILE G < K LOOP F := E*(A+B); G := (A+B)*(C+D); END LOOP; Algorithm ACBDE X Y FG K +* < Datapath PLA Latches Controller 7

Goal of High Level Synthesis From Behavioral specification at ‘System Level’ (Algorithms) To Structural implementation at ‘Register Transfer Level’ of Data path (ALU’s, REG’s, MUX’s) and Controller Optimize Area, Performance, Power, …Optimize Area, Performance, Power, … Abide by constraints,Abide by constraints, Generally restricted to a single processGenerally restricted to a single process Generally data path is optimized; controller is by-productGenerally data path is optimized; controller is by-product

Architectural versus Logic Synthesis Transform behavioral into structural view.Transform behavioral into structural view. Behavioral-level synthesis:Behavioral-level synthesis: –Architectural abstraction level (Algorithm). –Determine macroscopic structure (RTL). –Example of synthesis: major building blocks. Logic-level synthesis: Logic-level synthesis: –Logic abstraction level (Boolean Equations). –Determine microscopic structure (Gates). –Example of synthesis: logic gate interconnection.

Level of Automation must go up? Why?

Architectural-level synthesis motivation 1.Raise input abstraction level. o Reduce specification of details (hides them). o Extend designer base. o Self-documenting design specifications. o Ease modifications and extensions (Portability) 2. Reduce design time. o Rely on synthesis compilers to produce RTL o Faster to verify our designs at Arch Level 3.Explore and optimize macroscopic structure: o Series/parallel execution of operations. o Reduce power consumption (better algorithms)

Design Space Exploration Delay Area Arch I Arch II Arch III We consider here totally different architectures

13 Design Space Exploration: Multi Objective Optimization Area Latency Latency Max Area Max Cycle-time

Stages of architectural-level synthesis 1. Translate HDL or C/C++ models into:  Data Flow Graphs,  Sequencing Graphs. 2. Behavioral-level optimization:  Optimize abstract models independently from the implementation parameters. 3. Architectural synthesis and optimization:  Create macroscopic structure: data-path and control-unit. data-path and control-unit.  Consider area and delay information of the implementation. (on the global level)

HLS Flow Syntactic Analysis Optimization Scheduling/Resource Allocation Binding/Resource Sharing High-level Code Intermediate Representation Controller + Datapath Converts code to intermediate representation - allows all following steps to use language independent format. Determines when each operation will execute, and resources used Maps operations onto physical resources Front-end Back-end

Analysis and Parsing

Syntactic Analysis Definition: Analysis of code to verify syntactic correctnessDefinition: Analysis of code to verify syntactic correctness –Converts code into intermediate representation 2 steps2 steps –1) Lexical analysis (Lexing) –2) Parsing Syntactic Analysis High-level Code Intermediate Representation Lexical Analysis Parsing

Lexical Analysis Lexical analysis (lexing)Lexical analysis (lexing) –Breaks code into a series of defined tokens –Token: defined language constructs x = 0; if (y < z) x = 1; Lexical Analysis INT(0) INT(1) ID(x), ASSIGN, INT(0), SEMICOLON, IF, LPAREN, ID(y), LT, ID(z), RPAREN, ID(x), ASSIGN, INT(1), SEMICOLON

Lexing Tools Define tokens using regular expressions - outputs C code that lexes inputDefine tokens using regular expressions - outputs C code that lexes input –Common tool is “lex” /* braces and parentheses */ "[" { YYPRINT; return LBRACE; } "]" { YYPRINT; return RBRACE; } "," { YYPRINT; return COMMA; } ";" { YYPRINT; return SEMICOLON; } "!" { YYPRINT; return EXCLAMATION; } "{" { YYPRINT; return LBRACKET; } "}" { YYPRINT; return RBRACKET; } "-" { YYPRINT; return MINUS; } /* integers [0-9]+ { yylval.intVal = atoi( yytext ); return INT; }

Parsing Performs analysis on token sequence to determine correct grammatical structurePerforms analysis on token sequence to determine correct grammatical structure –Languages defined by context-free grammar Program = Exp Exp = Stmt SEMICOLON | IF LPAREN Cond RPAREN Exp | Exp Exp Cond = ID Comp ID Stmt = ID ASSIGN INT x = 0; if (y < z) x = 1; x = 0; x = 0; y = 1; if (a < b) x = 10; if (var1 != var2) x = 10; x = 0; if (y < z) x = 1; y = 5; t = 1; Grammar Correct Programs Comp = LT | NE

Parsing Program = Exp Exp = S SEMICOLON | IF LPAREN Cond RPAREN Exp | Exp Exp Cond = ID Comp ID S = ID ASSIGN INT Grammar Comp = LT | NE x = y; x = 3 + 5; ;; x = 5;; if (x+5 > y) x = 2; Incorrect Programs x = 5

Parsing Tools Define grammar in special languageDefine grammar in special language –Automatically creates parser based on grammar –Popular tool is “yacc” - yet-another-compiler- compiler program: functions { $$ = $1; } ; functions: function { $$ = $1; } | functions function { $$ = $1; } ; function: HEXNUMBER LABEL COLON code { $$ = $2; } ;

Overview of Hardware Synthesis converts the program text file into strings of tokens. Tokens can be specified by regular expressions. In the UNIX world, the “lex” tools are popular for this. grammarthe order and types syntax treeThe syntax of a programming language is specified by a grammar. (A grammar defines the order and types of tokens.) This analysis organized streams of tokens into an abstract syntax tree.

Overview of Hardware Synthesis analyze the semantics, or meanings, of the program. symbol table Generate a symbol table. Check for uniqueness of symbols and information about them. determine the order and organization of operations

Intermediate Representations DFG/CDFG

Intermediate Representation Parser converts tokens to intermediate representationParser converts tokens to intermediate representation –Usually, an abstract syntax tree x = 0; if (y < z) x = 1; d = 6; Assign if cond assign x 0 x 1 d 6 y < z

Intermediate Representation Why use intermediate representation?Why use intermediate representation? –Easier to analyze/optimize than source code –Theoretically can be used for all languages Makes synthesis back end language independentMakes synthesis back end language independent Syntactic Analysis C Code Intermediate Representation Syntactic Analysis Java Syntactic Analysis Perl Back End Scheduling, resource allocation, binding, independent of source language - sometimes optimizations too

Intermediate Representation Different TypesDifferent Types –Abstract Syntax Tree –Data Flow Graph (DFG) –Sequencing Graph (DFG with Source and Sink) –Control Flow Graph (CFG) –Control/Data Flow Graph (CDFG) CDFG  Combines control flow graph (CFG) and data flow graph (DFG)CDFG  Combines control flow graph (CFG) and data flow graph (DFG) ** + Data Flow Graph Control Flow Graph

Data Flow Graph DefinitionDefinition –A directed graph that shows the data dependencies between a number of functions –G = (V,E) Nodes (V): each node having input/output data portsNodes (V): each node having input/output data ports Arces (E): connections between the output ports and input portsArces (E): connections between the output ports and input ports –Semantics Fire when input data are readyFire when input data are ready Consume data from input ports and produce data to its output portsConsume data from input ports and produce data to its output ports There may be many nodes that are ready to fire at a given timeThere may be many nodes that are ready to fire at a given time

Data Flow Graphs DFGDFG –Represents data dependencies between operations x = a+b; y = c*d; z = x - y; + * - a b c d x y z

+ - x / ** sqrt x x b4ca2 - / X1X1 X2X2 Multiplication Constant Square root Division Nodes of DFG can be any operators, also very complex operators

Data flow graph construction original code: x  a + b; y  a * c; z  x + d; x  y - d; x  x + c; a b cd +* + + y x z x - x

Data flow graph construction original code: x  a + b; y  a * c; z  x + d; x  y - d; x  x + c; single-assignment form: x1  a + b; y  a * c; z  x1 + d; x2  y - d; x3  x2 + c;

Data flow graph construction single-assignment form: x1  a + b; y  a * c; z  x1 + d; x2  y - d; x3  x2 + c; a b cd +* + + y x3 z x1 - x2

36 Sequencing Graph * ** +< *** + Add source and sink nodes (NOP) to the DFG * NOP ** +< *** + Data Flow Graph (DFG) Sequencing Graph Required for some Scheduling Algorithms

Control Flow Graphs CFGCFG –Represents control flow dependencies of basic blocks –Basic block is section of code that always executes from beginning to end I.e. no jumps into or out of blockI.e. no jumps into or out of block acc = 0; for (i=0; i < 128; i++) acc += a[i]; if (i < 128) acc=0, i = 0 acc += a[i] i ++ Done

Control/Data Flow Graph CDFG  Combines CFG and DFGCDFG  Combines CFG and DFG –Maintains DFG for each node of CFG acc = 0; for (i=0; i < 128; i++) acc += a[i]; if (i < 128) acc=0; i=0; acc += a[i] i ++ Done acc 0 i 0 + a[i] acc + i 1 i

Control/Data Flow Graph Definition – A directed graph that represents the control dependencies among the functions branch fall-through – G=(V,E) Nodes (V) –Encapsulated DFG –Decision Arcs (E) –flow of the controls Very similar to FSMD – Operation rectangles (instructions) can be vary complicated – Diamonds for predicates can be very complicated and require many clock pulses to complete.

CDFG Example fun0(); if (cond1) fun1(); else fun2(); fun3(); switch(test1) { case 1: fun4(); break; case 2: fun5(); break; case 3: fun6(); break; } fun7(); fun0 cond1 fun3 fun2 fun1 fun5fun6fun4 fun7 test1 YN

Summary Data Flow Graph Data Flow Graph (DFG) –models data dependencies. –Does not require that nodes be fired in a particular order. operations –Models operations in the functional model—no conditionals. –Allocation and Mapping –Scheduling – ASAP, ALAP, List-based scheduling Control/Data Flow Graph Control/Data Flow Graph –Represents control dependencies

High-Level Synthesis: Optimization

Synthesis Optimizations After creating CDFG, high-level synthesis optimizes graphAfter creating CDFG, high-level synthesis optimizes graph GoalsGoals –Reduce area –Improve latency –Increase parallelism –Reduce power/energy 2 types2 types –Data flow optimizations –Control flow optimizations

Behavioral Optimization

Data Flow Optimizations Tree-height reductionTree-height reduction –Generally made possible from commutativity, associativity, and distributivity d a b c a b cd + + * a b cd + * + a b cd

Tree-height reduction using commutativity and associativity x = ( a + (b * c ) ) + d x = (a +d) + (b * c) x = ( a + (b * c ) ) + d x = (a +d) + (b * c) No Change in Resources

Tree-height reduction using distributive.. x = a * (b * c * d +e) x = (a * b) * (c * d) + (a e); x = a * (b * c * d +e) x = (a * b) * (c * d) + (a e); Increase in Resources Required

Data Flow Optimizations Operator Strength ReductionOperator Strength Reduction –Replacing an expensive (“strong”) operation with a faster one –Common example: replacing multiply/divide with shift b[i] = a[i] * 8; b[i] = a[i] << 3; a = b * 5; c = b << 2; a = b + c; 1 multiplication 0 multiplications a = b * 13; c = b << 2; d = b << 3; a = c + d + b;

Data Flow Optimizations Constant propagationConstant propagation –Statically evaluate expressions with constants x = 0; y = x * 15; z = y + 10; x = 0; y = 0; z = 10;

Examples of propagation First Transformation type: Constant propagation:First Transformation type: Constant propagation: –a = 0, b = a +1, c = 2 * b, –a = 0, b = 1, c = 2, Second Transformation type: Variable propagation: Second Transformation type: Variable propagation: –a = x, b = a +1, c = 2 * a, –a = x, b = x +1, c = 2 * x,

Data Flow Optimizations Function SpecializationFunction Specialization –Create specialized code for common inputs Treat common inputs as constantsTreat common inputs as constants If inputs not known statically, must include if statement for each call to specialized functionIf inputs not known statically, must include if statement for each call to specialized function int f (int x) { y = x * 15; return y + 10; } for (I=0; I < 1000; I++) f(0); … } Treat frequent input as a constant int f_opt () { return 10; } for (I=0; I < 1000; I++) f_opt(0); … } int f (int x) { y = x * 15; return y + 10; }

Data Flow Optimizations Common sub-expression eliminationCommon sub-expression elimination –If expression appears more than once, repetitions can be replaced a = x + y; b = c * 25 + x + y; a = x + y; b = c * 25 + a; x + y already determined

Data Flow Optimizations Dead code eliminationDead code elimination –Remove code that is never executed May seem like stupid code, but often comes from constant propagation or function specializationMay seem like stupid code, but often comes from constant propagation or function specialization int f (int x) { if (x > 0 ) a = b * 15; else a = b / 4; return a; } int f_opt () { a = b * 15; return a; } Specialized version for x > 0 does not need else branch - “dead code”

Data Flow Optimizations Code motion (hoisting/sinking)Code motion (hoisting/sinking) –Avoid repeated computation for (I=0; I < 100; I++) { z = x + y; b[i] = a[i] + z ; } z = x + y; for (I=0; I < 100; I++) { b[i] = a[i] + z ; }

Control Flow Optimizations Loop UnrollingLoop Unrolling –Replicate body of loop May increase parallelismMay increase parallelism for (i=0; i < 128; i++) a[i] = b[i] + c[i]; for (i=0; i < 128; i+=2) { a[i] = b[i] + c[i]; a[i+1] = b[i+1] + c[i+1] }

Control Flow Optimizations Function InliningFunction Inlining –Replace function call with body of function Common for both SW and HWCommon for both SW and HW –SW - Eliminates function call instructions –HW - Eliminates unnecessary control states for (i=0; i < 128; i++) f( b[i], c[i] ); a[i] = f( b[i], c[i] );.. f (int a, int b) int f (int a, int b) { return a + b * 15; } for (i=0; i < 128; i++) a[i] = b[i] + c[i] * 15;

Control Flow Optimizations Conditional ExpansionConditional Expansion –Replace if with logic expression Execute if/else bodies in parallelExecute if/else bodies in parallel y = ab if (a) x = b+d else x =bd y = ab x = a(b+d) + a’bd y = ab x = y + d(a+b) Can be further optimized to:

High-level Synthesis: Summary

Main Steps Syntactic Analysis Optimization Scheduling/Resource Allocation Binding/Resource Sharing High-level Code Intermediate Representation Controller + Datapath Converts code to intermediate representation - allows all following steps to use language independent format. Determines when each operation will execute, and resources used Maps operations onto physical resources Front-end Back-end

60 Scheduling, Allocation and Assignment Techniques are well understood and mature

Synthesis in the Temporal Domain ASAP Here we use sequencing graph

Synthesis in the Spatial Domain First multiplier Second multiplier Third multiplier Fourth multiplier First ALU Second ALU Solution Four Multipliers Two ALUs Four Cycles

Main Steps Front-end (lexing/parsing) converts code into intermediate representationFront-end (lexing/parsing) converts code into intermediate representation –We looked at CDFG Scheduling assigns a start time for each operation in DFGScheduling assigns a start time for each operation in DFG –CFG node start times defined by control dependencies –Resource allocation determined by schedule Binding maps scheduled operations onto physical resourcesBinding maps scheduled operations onto physical resources –Determines how resources are shared Big picture:Big picture: –Scheduled/Bound DFG can be translated into a datapath –CFG can be translated to a controller –=> High-level synthesis can create a custom circuit for any CDFG!

64

Example Optimize thisOptimize this x = 0; y = a + b; if (x < 15) z = a + b - c; else z = x + 12; output = z * 12;