© 2008, Renesas Technology America, Inc., All Rights Reserved 1 Course Introduction  Purpose:  This course provides an overview of the SH-2A 32-bit RISC CPU core built into newer microcontrollers in the popular SH-2 series  Objectives:  Gain a basic overview of the SH-2A CPU architecture  Understand key features of this powerful 32-bit RISC CPU  Learn about the internal CPU registers  Acquire knowledge about the CPU’s addressing modes  Explore the SH-2A instruction set, including the new instructions added to those of the SH-2 set  Content:  15 pages  3 questions  Learning Time:  35 minutes

© 2008, Renesas Technology America, Inc., All Rights Reserved 2 Overview of SH-2A CPU Core  General SH-2A: The 32-bit RISC CPU for newer SH-2 series Renesas microcontrollers that...  Is a member of the SuperH ® family  Powers the SH7206 device and others  Operates at clock speeds up to 200MHz  Executes up to two instructions per cycle –Delivers up to 360 MIPS performance  Software  Has RISC-type instruction set and addressing modes – Is based on “C” – Includes delayed branch instructions  Includes 16-bit fixed-length basic instructions for high code density  Is upwardly software compatible with SH-1/SH-2 CPUs at object-code level.  Adds 32-bit instructions for high performance  Incorporates new bit-manipulation instructions

© 2008, Renesas Technology America, Inc., All Rights Reserved 3 SH-2A CPU Overview  Hardware  Has a superscalar and Harvard architecture  Executes two instructions/cycle  Is a load-store design  Has a five-stage pipeline  Includes 16 general-purpose 32-bit registers  Uses register banks for fast interrupt response  Has built-in hardware multiplier-accumulate unit (MAC) for DSP-type operations  Provides a 4GB address space  Offers an optional FPU: SH2A-FPU core 5-stage Pipeline (*Two instructions are fetched and executed simultaneously) System Registers Clock Hardware Multiplier General Registers Control Registers Register Banks SH-2A CPU Superscalar* RISC Design CPU Instruction Fetch Bus CPU Data Fetch Bus On-chip Cache FPU (SH2A-FPU only)  Support  Is supported by a comprehensive set of Renesas software and hardware tools  Is also supported by many products and services from a large community of vendors

© 2008, Renesas Technology America, Inc., All Rights Reserved 4 SH-2A CPU Model R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R BO CS - - -M Q I[3:0] - - S T 031 Status Register (SR) GBR 031 Global Base Register (GBR) VBR 031 Vector Base Register (VBR) TBR 031 Jump Table Base Register (TBR) MACH 031 Multiply and accumulate registers MACL PR Procedure Register (PR) PC Program Counter (PC) 031 0

© 2008, Renesas Technology America, Inc., All Rights Reserved Load-Store Architecture  Arithmetic instructions have operands in the register  A generous register set is required and provided  Operands must be loaded from memory  Execution time is very fast and predictable.  Local arithmetic execution time is independent of data path  Standard data length is 32 bits (longword)  Any 8- or 16-bit data is sign-extended for arithmetic operations, or zero-extended for logic operations Operated Upon Memory Register

© 2008, Renesas Technology America, Inc., All Rights Reserved 7 Immediate Data  Byte immediate data is stored in instruction code  Word or longword immediate data is located in memory tables (literal pool) accessed via a PC-relative addressing mode MOV instruction  SH-2A CPU allows 17- to 28-bit immediate data to be stored in the instruction code  For 21- to 28-bit data, an OR or AND instruction must be executed after the transfer instruction

© 2008, Renesas Technology America, Inc., All Rights Reserved Addressing modes define how/where to find operands SH-2A: A Single-Address Machine  Because the SH-2A is a SINGLE-ADDRESS machine...  At least one operand is always stored in a register  The other operand is defined by the addressing mode  The addressing mode defines the Effective Address (EffA) calculation Exception: MAC Example: Store contents of register R1 in memory; address of memory is in R2 MOV.L - Source operand is general register R1 - Destination is memory; address is in R2 (Addressing mode: Register indirect)

© 2008, Renesas Technology America, Inc., All Rights Reserved Addressing Modes  Register direct:Rn  Register  Register indirect with  Register indirect with  Register indirect  Indexed register  GBR indirect with  Indexed GBR  TBR duplicate indirect with  PC indirect with  PC relativedisp:8 disp:12 Rn  Immediate:#imm:20 #imm:8 #imm:3 Used by standard arithmetic & logic operations Used for array handling & popping values from stack Used to push values onto the stack Great for accessing C/C++ structure contents Efficient calling of functions via a function pointer table Used to access 16-bit and 32-bit constant data from memory tables/literal pools Facilitates far branching to anywhere in address space 20-bit immediate data can be held in a 32-bit instruction 8-bit and 3-bit (bit instructions) data can be held in 16-bit instructions

© 2008, Renesas Technology America, Inc., All Rights Reserved 10 New Instructions - Part 1  Immediate data transfers  MOVI20, MOVI20S –MOVI20 transfers 20-bit immediate data to a register –MOVI20S instruction enables the generation of a 28-bit address, making it possible to specify on-chip addresses up to 256MB  Structure-access instructions using 12-bit displacement  e.g., MOV.B/W/L  Bit-manipulation instructions operating on memory and general registers  e.g., BAND.B Rn),  BCLR.B #imm:3, Rn

© 2008, Renesas Technology America, Inc., All Rights Reserved 11 New Instructions - Part 2  Multiplication result instruction  MULR R0, Rn  Store the lower 32-bits of a 32x32-bit multiply in Rn  Batch division of 32-bit signed and unsigned data  DIVS, DIVU  Saturation value comparison instructions  CLIPS, CLIPU  Barrel shift instructions  SHAD, SHLD  Multiple register save/restore instructions  MOVML, MOVMU

© 2008, Renesas Technology America, Inc., All Rights Reserved 12 New Instructions - Part 3  T-bit inversion and transfer instructions  E.g. MOVRT, NOTT  Register banking instructions  RESBANK, STBANK, LDBANK  Reverse stack transfer instructions  MOV.B/W/L  R0  Unconditional branch instructions with no delay slot  JSR/N, RTS/N  Cache prefetch instruction  PREF

© 2008, Renesas Technology America, Inc., All Rights Reserved Features of Instruction Set Types of Operations:  Data transfer  Arithmetic  Logic  Shift / Rotate  System control  Program flow control  Bit manipulation  Floating point EXTU.BR0,R0 MOV.LL278+14,R3 ADDR0,R3 EXTU.BR0,R0 MOV.LL278+22,R1 ADD#1,R0 EXTU.BR0,R0 MOV#6,R3 CMP/GTR3,R0 BFL268

© 2008, Renesas Technology America, Inc., All Rights Reserved Data Transfer Instruction: Move  MOV: General move to / from registers;  byte, word and longword operand  No modification of status register (in contrast to H8 series)  Immediate 8-bit: MOV.B #value:8,Rn  Immediate 20-bit: MOVI20 #value:20,Rn  Immediate 16-bit:  address: displ*2 + PC  Immediate 32-bit:  address: displ*4 + PC In Literal Pools R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R (SP) Memory or I/O In Instruction

© 2008, Renesas Technology America, Inc., All Rights Reserved Arithmetic/Logic Instructions  ADD, SUB  Compare: CMP  Divide support: DIV  Multiply Rn * RmMUL   Negate: NEG  AND, OR, TST, XOR  Addressing modes for AND, OR, TST, XOR: –AND Rm,Rn, AND #dd:8,Rn, AND  TAS:  ;"test and set" operates on byte and T-bit  NOT:  NOT Rm,Rn; ~Rm Rn

© 2008, Renesas Technology America, Inc., All Rights Reserved Shift/Rotate Instructions  Shift / rotate one bit  Shift / rotate one bit with T-bit  Barrel shift  Shift n bit(s), n=2, 8, 16  n=2: x4 or /4  n=8: shift by one byte (or x256, /256)  n=16: shift by one word (or x65536, /65536) >> << Note: These instructions are only suitable for unsigned arithmetic!

© 2008, Renesas Technology America, Inc., All Rights Reserved System Control Instructions  Set/clear T-bit: SETT, CLRT  MAC clear: CLRMAC  Load/Store system registers (SR, GBR, VBR): LDS, STS  Copy contents of system register to/from any general-purpose register or memory, using addressing (stack compatible)  Load/Store control registers (MAC, PR): LDC, STC  Copy contents of control registers to/from any general-purpose register or memory, using addressing (stack compatible)  Sleep (either standby or sleep)  Return from exception: RTE  Save and restore register bank  TRAPA

© 2008, Renesas Technology America, Inc., All Rights Reserved Program Flow Instructions  Conditional & unconditional delayed branches (same as SH-2 CPU)  Conditional branch coding and handling sequence:  T-bit handling with COMPARE instruction  Result of condition is tested in T-bit  Then branch conditional  Unconditional branch with no delay slot (added instruction)  A subroutine call instruction causes the hardware to:  Copy PC contents in PR  Put new value into PC  Go to next instruction  A return from subroutine instruction causes the hardware to:  Copy PR contents in PC  Go to next instruction  Exception handling

© 2008, Renesas Technology America, Inc., All Rights Reserved 20 Bit Manipulation Instructions  Logical  AND, OR, XOR, NOT-AND, NOT-OR  Bit set  Bit clear  Bit store  Bit load  Bit NOT load

© 2008, Renesas Technology America, Inc., All Rights Reserved Boosts program execution speed and reduces code size! Subroutine Calls  Instructions: BSR, JSR, RTS  Hardware support for single-level subroutine calls  Multiple-level calls require support: "PUSH" and "POP" of previous PC under software control Sequence:  Enter subroutine (BSR/JSR):  Hardware: Copy PC to PR  Load new value to PC  (Software: Push PR to stack)  Execute next instruction ...code...  Exit subroutine:  (Software: Pop PR from stack)  Hardware: RTS instruction  Copy PR to PC  Continue PR Procedure Register Program Counter = One-level-deep buffer! PC

© 2008, Renesas Technology America, Inc., All Rights Reserved 23 Course Summary  Overview of SH-2A RISC CPU features, architecture  Internal CPU registers  Addressing modes  Instruction set