ITEC 352 Lecture 23 CPU analysis. CPU Review Pipelining –Long –Short –Bubbles –Branches –Efficiency.

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Presentation transcript:

ITEC 352 Lecture 23 CPU analysis

CPU Review Pipelining –Long –Short –Bubbles –Branches –Efficiency

CPU Outline CPU –History –Evolution

CPU Intel pins –How does this compare w/ your breadboard? 7 registers 78 instructions 65,536 bytes of addressable memory Programmable stacks As described in the manual

CPU Registers A-H or 0-7 –A was the accumulator (where results were stored) Pairs –Some instructions required certain registers to be used –I.e. B and C would be used for a certain instruction Has a PSW (1 byte) in register A that stores the state of the machine

CPU Memory 64k possible memory (2^16) 8 bit cpu (no direct way to handle 16 bits) Stack pointer –Programmer maintained –Instruction augmented Program counter –16 bits to tell CPU where to get next instruction Instructions could be 1,2, or 3 bytes Cautions against storing data and instructions together

CPU Addressin g Direct –Uses a register Immediate –Instruction then address in memory Stack –Convention for first / second places to get memory (pairs)

CPU Assembly Style –LabelCodeOperand ;Comment Data –Hex, Binary, Octal Instructions –+,-,*,mod,and,or,not,shr,shl,xor –mvi register address –jmp address All arithmetic operations assume 2s complement format

CPU Assembly(2 ) DW,DB,DS –Define a place in memory MOV, LDAX, STAX (Load/Store register A) CMP = Compare register / memory w/ register A DAD –The double add (16 bit on an 8 bit) Many others, but same complexity level

CPU Stack push registerPair pop registerPair inx register (increment pointer) Put / Store registers / memory

CPU Capabilities ? What can a 2 Mhz CPU do? Not an intel CPU. However 1.76Mhz and ~15 MMapped registers

CPU GFX

CPU Pentium 1

CPU Pentium 3 P3

CPU i7 CPU

CPU Takeaway CPU development is amazing Double edged sword When and why to goto low level

CPU Summary CPU