High-Level Synthesis-II Virendra Singh Indian Institute of Science Bangalore IEP on Digital System IIT Kanpur

Dec 18, Architectural Synthesis Architectural Level Abstraction Datapath Controller Architectural Synthesis Constructing the macroscopic structure of a digital circuit starting from behavioural models that can be captured from Data flow or Sequencing Graph

Dec 18, Architectural Synthesis Objective Area Cycle time Latency Throughput Worst case bound Evaluation Architectural Exploration

Dec 18, Architectural Synthesis Architectural synthesis tool can select an appropriate design point according to some user specific criterion and construct corresponding user specific Datapath and Controller Circuit Specification for Architectural Synthesis Behavioural circuit model Details about resources being used and constraints Capture by Sequencing Graph

Dec 18, Architectural Synthesis Resources Functional Resources Primitive Resources Application Specific Resources Memory Resources Interface Resources

Dec 18, Architectural Synthesis Circuit Specification Sequencing Graph A set of functional resources, fully characterized in terms of area and execution delay A set of constraints

Dec 18, Architectural Synthesis Computation: Differential Equation Solver xl = x + dx ul = u – (3*x*u*dx) – (3*y*dx) c = xl < a Data Flow Graph (DFG): represent operation and data dependencies

Dec 18, Data Flow Graph * * * + * * * +< x 3 u dx 3 y u x u y a c xl yl ul

Dec 18, Sequencing Graph * * * + * * * +< - - NOP

Dec 18, Hierarchical Sequencing Graph NOP * CALL + * *+ NOP a.0 a.3 a.2 a.1 a.4 a.n b.0 b.n b.2 b.1

Dec 18, Architectural Synthesis Architectural Synthesis and optimization consistes of two stages 1.Placing the operation in time and in space, i.e., determining their time interval of execution and binding to resources 2.Determining detailed interconnection of the datapath and the logic-level specifications of the control unit

Dec 18, Temporal Domain: Scheduling Delay D = {d i ; i = 0,1, 2, ….. n} Start time T ={t i ; i= 0, 1, …., n) Scheduling: Task of determining the start timing, subject to preceding constraints specified by sequencing graph Latency λ = t n – t 0

Dec 18, Temporal Domain: Scheduling A scheduled sequencing graph is a vertex-weighted sequencing graph, where each vertex is labeled by its start time OperationStart time V1,V2, v6,v8, v10 1 V3, v7, v9,v112 V43 V54  Chaining

Dec 18, Temporal Domain: Scheduling * * * + * * * +< - - NOP TIME 1 TIME 2 TIME 3 TIME 4

Dec 18, Temporal Domain: Scheduling * * * + * * * + < - - NOP TIME 1 TIME 2 TIME 3 TIME 4 TIME 5 TIME 6 TIME 7

Dec 18, Spatial Domain: Binding A fundamental concept that relates operation to resources is binding Resource types Resource sharing Simple case of binding is a dedicated resources

Dec 18, Spatial Domain: Binding β(v1) = (1,1) β(v2) = (1,2) β(v3) = (1,3) β(v4) = (2,1) β(v5) = (2,2)..

Dec 18, Spatial Domain: Binding * * * + * * * +< - - NOP TIME 1 TIME 2 TIME 3 TIME 4

Dec 18, Spatial Domain: Binding A necessary condition for resource binding to produce a valid circuit implementation is that operation corresponding to the shared resource do not execute concurrently A resource binding can be represented by a labeled hyper-graph, where the vertex set V represents operations and the edge set E β represents the binding of the operation to the resources

Dec 18, Spatial Domain: Binding * * * + * * * +< - - NOP TIME 1 TIME 2 TIME 3 TIME 4 n (1,1)(1,2) (1,3)(1,4) (2,2) (2,1)

Dec 18, Spatial Domain: Binding * * * + * * * + < - - NOP TIME 1 TIME 2 TIME 3 TIME 4 0 n

Dec 18, Sequencing Graph * * * + * * * +< - - NOP

Dec 18, Hierarchical Sequencing Graph NOP * CALL + * *+ NOP a.0 a.3 a.2 a.1 a.4 a.n b.0 b.n b.2 b.1 (1,2) (1,1) (2,1)

Dec 18, Synchronization * SYN ++ NOP 0 1 a 2 3 n

Dec 18, Synchronization * SYN ++ NOP 0 1 a 2 3 n * SYN ++ NOP 0 1 a 2 3 n

Dec 18, Synchronization * SYN + + NOP 0 1 a 2 3 n

Dec 18, Area/Performance Estimation Accurate area and performance estimation is not an easy task Schedule: provides latency Binding: provides information about the area

Dec 18, Retiming + Host δ + δ + δδ

Dec 18, Retiming Vg Vh Va Vf Vb Ve VcVd

Dec 18, Retiming Vg Vh Va Vf Vb Ve VcVd Delay = 24

Dec 18, Retiming Vg Vh Va Vf Vb Ve VcVd

Dec 18, ASAP Scheduling * * * + * * * +< - - NOP TIME 1 TIME 2 TIME 3 TIME 4

Dec 18, ASAP Scheduling ASAP(Gs(V,E)){ Schedule v0 by setting t 0 s = 1; repeat{ select vertex v i whose predecessors are all scheduled; schedule vi by setting ti s = max{tjs+ dj} } untill (v n is scheduled) return t s }

Dec 18, ALAP Scheduling * * * + * ** +< - - NOP TIME 1 TIME 2 TIME 3 TIME 4

Dec 18, Scheduling under Timing Constraints Scheduling under latency constraints Absolute constraints on start time Relative constraints Relative timing constraints are positive integers specified for some operation pair vi, vj A minimum timing constraint l ij ≥ 0 requires t j ≥ t i +l ij A maximum timing constraint u ij ≤ 0 requires t j ≤ t i +u ij

Dec 18, Constraint Graph ** ++ NOP n Min Time 4 Max Time 3

Dec 18, Constraint Graph 0 4 ** ++ NOP n Min Time 4 Max Time 3 ** ++ NOP n

Dec 18, Relative Scheduling Scheduling under unbounded delay The anchors of a constraint graph G(V,E) consists of the source vertex v0and all vertices with unbounded delay Redundant anchor

Dec 18, Sequencing Graph 1 3 * SYN ++ NOP 0 a 2 n

Dec 18, Scheduling with Resource Constraint Scheduling under resource constraints computing area/latency trade-off points Problems Intractable problem Area-performance trade-off points are affected by the other factors - non-resource dominated circuits

Dec 18, Scheduling with Resource Constraint ILP Formulation Binary decision variable X = {x il } 1.Start time of each operation is unique Σ l x il = 1 2. Sequencing relations represented by Gs(V,E) must be satisfied Σ l x il ≥ Σ l xjl + d j 3. Resource bound must be met at every schedule step Σ k Σ m x im ≤ a k

Dec 18, ILP Formulation All operation must start only once x 0,1 = 1 x 1,1 = 1 x 2,1 = 1 x 3,2 = 1 x 4,3 = 1 x 5,4 = 1 x 6,1 + x 6,2 = 1 x 7,2 + x 7,3 = 1 x 8,1 + x 8,2 +x 8,3 = 1 x 9,2 + x 9,3 +x 9,4 = 1 x 10,1 + x 10,2 +x 10,3 = 1 x 11,2 + x 11,3 +x 11,4 = 1 x n,5 = 1

Dec 18, ILP Formulation Constraints – based on sequencing (more than one starting time for at least one operation) 2 x 7,2 + 3 x 7,3 – x 6,1 – 2 x 6,2 – 1 ≥ 0 2 x 9,2 + 3 x 9,3 + 4 x 9,4 – x 8,1 – 2 x 8,2 – 3 x 8,3 – 1 ≥ 0 2 x 11,2 + 3 x 11,3 + 4 x 11,4 – x 10,1 – 2 x 10,2 – 3 x 10,3 – 1 ≥ 0 4 x 5,4 – 2 x 7,2 – 3 x 7,3 – 1 ≥ 0 5 x n,5 – 2 x 9,2 – 3 x 9,3 – 4 x 9,4 – 1 ≥ 0 5 x n,5 – 2 x 11,2 – 3 x 11,3 – 4 x 11,4 – 1 ≥ 0

Dec 18, ILP Formulation Resource Constraints x 1,1 + x 2,2 + x 6,1 + x 8,1 ≤ 2 x 3,2 + x 6,2 + x 7,2 + x 8,2 ≤ 2 x 7,3 + x 8,3 ≤ 2 x 10,1 ≤ 2 x 9,2 + x 10,2 + x 11,2 ≤ 2 x 4,3 + x 9,3 + x 10,3 + x 11,3 ≤ 2 x 5,4 + x 9,4 +x 11,4 ≤ 2

Dec 18, ILP Formulation Optimize Σ i Σ l l.x il x 6,1 + 2 x 6,2 + 3 x 7,2 + 3 x 7,3 + x 8,1 + 2 x 8,2 + 3 x 8,3 + 2 x 9,2 + 3 x 9,3 + 4 x 9,4 + x 10,1 + 2 x 10,2 + 3 x 10,3 + 2 x 11,2 + 3 x 11,3 + 4 x 11,4

Dec 18, Resource Sharing Resource sharing: Assignment of resource to more than one operation Goal: Reduce area Resource binding: explicit definition of mapping between resources and operation Binding may imply some resources are shared

Dec 18, Optimum Scheduling under Resource Constraint * * * + * ** + < - - NOP TIME 1 TIME 2 TIME 3 TIME 4

Dec 18, Scheduled Sequencing Graph * * * + * ** + < - - NOP TIME 1 TIME 2 TIME 3 TIME 4

Dec 18, Compatibility Graph

Dec 18, Conflict Graph

Dec 18, Transitive orientation of Compatibility Graph

Dec 18, Resource Sharing in Non- Hierarchical Seq. Graph Searching for binding compatible Σ r b ir = a Σbir Σ xim ≤ 1

Dec 18, Scheduled and Bound Sequencing Graph * * * + * ** + < - - NOP TIME 1 TIME 2 TIME 3 TIME 4 (1,1) (1,2) (2,1) (2,2)