D75P 34 – HNC Computer Architecture Lecture 13 The Fetch-Decode-Execute Cycle [2]. © C Nyssen/Aberdeen College 2003 All images © C Nyssen/Aberdeen College except where stated Prepared 6/01/04

Let’s begin our assessment example by reviewing the diagram of the CPU from Outcome 2. It is important to always remember the function of the five main registers involved – the Program Counter, the MAR, the MDR, the Instruction Register and the Accumulator. Sometimes an extra, General Purpose, register will be involved as well.

To begin, all the instructions are loaded into the RAM. You will be given a table, or diagram, representing the RAM already containing data and instructions.

Note that the lines of code will correspond exactly to the entries in the matching RAM addresses. Although the assembly code is written in mnemonics, it is stored as numeric values. For example, LDX [15] on line 0006 means exactly the same thing as 30 – [15]. For assessment purposes you can use either numbers or mnemonics.

The CPU now fetches each instruction in turn, decodes and executes it The CPU now fetches each instruction in turn, decodes and executes it. We will begin with line 0005. 0005 10-16 0005

The FDE Cycle has 3 distinct phases – FETCH - the CPU collects the instruction from RAM DECODE - the Control Unit figures out what to do with it EXECUTE - the instruction is carried out. The FETCH and DECODE phases never vary. The EXECUTE phase may be different each time, because it depends on what the instruction was! For this example the program counter starts from 0005.

FETCH First the Program Counter copies its’ contents to the MAR. Whenever a new value enters the MAR, this is the signal for it to point to the matching RAM address using the Address Bus. The contents of 0005 are dumped on the Data Bus, and brought back to the CPU via the MDR. The contents of the MDR now get transferred to the Instruction Register, ready to be decoded.

DECODE The Decoder in the Control Unit takes the instruction and splits it into the two parts – the opcode and the operand. In this example the opcode LDA or 10 tells us to load the accumulator with data. The Operand 16 tells us where the data will come from. Remember to increment the PC!

                                                       EXECUTE This will vary between instructions. In this case we are loading the accumulator with a value taken from RAM location 16. To bring the data back, we first have to set up the MAR again so it is pointing at the correct cell. The 16 is put in the MAR, triggering it to point to RAM address 16.

When the pointer hits address 16, this is the signal for it to dump the contents onto the Data Bus. So the value 0F is sent back to the MDR. The whole instruction was to Load the Accumulator, so the 0F is copied there. Read upwards to find the Finishing Values, which will of course be the Starting Values for the next instruction.

FETCH The Program Counter (now 0006) copies its’ contents to the MAR. The address bus points to location 0006, which is the signal to dump the contents 30 – [15] on the Data Bus. This is brought back to the CPU via the MDR. The contents of the MDR now get transferred to the Instruction Register, ready to be decoded.

DECODE The instruction is split into the opcode 30 (or LDX) and the operand [15]. The PC increments by 1. The Operand [15] tells us where the data will come from. The opcode LDX or 30 tells us to load the X register with data. Note however that the operand is in [square brackets], telling us that this is an indirect address.

EXECUTE To bring the contents back, we first have to set up the MAR again so it is pointing at the correct cell. The [15] is put in the MAR, triggering it to point to RAM address 15. The contents of 15 are returned to the MDR as normal. Because the 15 was an indirect address, however, the contents of that cell are neither a data value nor instruction, but another address.

We now use the 14 to set up the MAR again We now use the 14 to set up the MAR again. In turn, it will point to address 0014 and trigger the data bus to retrieve the contents. Having finally collected the data, we can complete the whole instruction, which was to Load the X Register with the relevant value. The 12 now gets copied to the GP register.

Read upwards to find the Finishing Values, which will of course be the Starting Values for the next instruction. Note that the Accumulator value has not changed, as nothing has happened yet to overwrite the 0F.

FETCH The PC copies its’ contents to the MAR, which is triggered to point to RAM location 0007. The instruction 20 –(X) is taken from RAM address 0007 and copied to the MDR. It is then passed on to the IR to be decoded.

DECODE The 20 –(X) is decoded and the PC incremented by 1. The 20, or SUB, means subtract the contents of the X register from the value currently in the Accumulator.

EXECUTE The 12 from the GP register is subtracted from the 0F in the Accumulator, giving the result -3. As usual, read upwards to find the Finishing Values.

FETCH The Program Counter (now 0008) copies its’ contents to the MAR. The address bus points to location 0008, which is the signal to dump the contents 90-0A on the Data Bus. This is brought back to the CPU via the MDR. The contents of the MDR now get transferred to the Instruction Register, ready to be decoded.

DECODE The 90-0A is decoded and the PC incremented by 1. The 90, or JLE, means jump to another point in the program if the Accumulator contents are zero or less. The 0A tells us at which point the program execution should jump to.

EXECUTE At this point the ALU has to make a logical decision. Is the value 0 or less? If this condition is false, no further action is required and the program continues as normal. But in this case, the condition evaluates as true, as –3 is less than zero. So the program flow jumps to line 000A. Whenever a jump or branch takes place, the Program Counter is adjusted so that the next line of code to be run will be the correct one! As usual, read upwards to find the Finishing Values.

FETCH The Program Counter (now 000A) copies its’ contents to the MAR. The address bus points to location 000A, which is the signal to dump the contents 50-19 on the Data Bus. This is brought back to the CPU via the MDR. The contents of the MDR now get transferred to the Instruction Register, ready to be decoded.

DECODE The 50-19 is decoded and the PC incremented by 1. The 50, or STA means store the contents of the Accumulator in some specified RAM location... …and the 19 tells us where.

EXECUTE As we are sending information back to the RAM, we must first set up the pointer to access the correct address. The 19 is used to point to RAM address 0019 and prepare the chip for writing. In order to send the –3 along the Data Bus, it must first be put into the MDR. It can then be transferred and safely stored away in the RAM chip. The existing value, 0000, is overwritten.

The complete solution to the question.

Summary FETCH – PC value is copied to the MAR. The MAR points to the correct RAM address. Contents of that address are brought back to MDR. Contents are passed to the IR for decoding. DECODE Instruction is split into an Opcode and Operand. PC is incremented by 1. EXECUTE This may involve setting up the MAR again, loading or moving values, resetting the Program Counter or performing arithmetic or logic operations.