Timing Analysis Section 2.4.2

Delay Time Def: Time required for output signal Y to change due to change in input signal X Up to now, we have assumed this delay time has been 0 seconds. t=0

Delay Time In a “real” circuit, it will take tp seconds for Y to change due to X t=0t=tp tp is known as the propagation delay time

Timing Diagram We use a timing diagram to graphically represent this delay Horizontal axis = time axis Vertical axis = Logical level axis (Logic One or Logic Zero)

Timing Diagram We see a change in X at t=0 causes a change in Y at t=tp Horizontal axis = time axis Vertical axis = Logical level axis (Logic One or Logic Zero)

Timing Diagram We also see a change in X at t=T causes another change in Y at t=T+tp We see that logic circuit F causes a delay of tp seconds in the signal

Simple Example – Not Gate Let tp=2 ns Where ns = nanosecond = 1x10 -9 seconds 2ns

Simple Example – 2 Not Gates Let tp=2 ns Total Delay = 2ns + 2ns = 4ns 2ns 4ns

Simple Example – 2 Not Gates Notes: Time axis is shared among signals Logic levels (1 or 0) are implied, not shown

Simple Example – 2 Not Gates Sometimes dashed vertical lines are added to aid reading diagram 2ns

Where does this delay come from? Circuit Delay

All electrical circuits have intrinsic resistance (R) and capacitance (C). Let’s analyze a simple RC circuit

Circuit Delay – Simple RC Circuit Vout Vin Note:

Circuit Delay – Example Vout Vin Let R=1ohm, C=1F, so that RC=1 second Time Delay is 0.7s or 700 ms for 0.5Vdd Time Delay is 2.3s for 0.9Vdd Time Delay is 4.6s for 0.99 Vdd

How do we relate this to logic diagrams?

Def: tplh tplh = low-to-high propagation delay time This is the time required for the output to rise from 0V to ½ VDD tplh

Def: tphl Tphl = high-to-low propagation delay time This is the time required for the output to fall from Vdd to ½ VDD tphl

Def: tp (propagation delay time) Let’s define tp = propagation delay time as This will be the “average” delay through the circuit

Gate Delay – Simple RC Model Ideal gate with RC network Equivalent model with Gate delay of tp_not Ideal gate with tp=0 delay RC network Tp=tp_not

Gate Delay - Example X 025ns 05ns30ns Y 5ns tp_not We indicate tp on the gate

Combinational Logic Delay Shortest delay Longest delay Longest delay = 20ns Shortest delay = 5ns This circuit has multiple delay paths A-Y = 5ns+5ns+5ns=15ns B-Y = 5ns+5ns+5ns+5ns=20ns C-Y = 5ns+5ns+5ns=15ns D-Y = 5ns

Combinational Logic Delay Shortest delay Longest delay Longest delay = 20ns We’ll use the longest delay to represent the logic function F. Let’s call it Tcl for time, combinational logic

Combinational Logic (CL) Cloud Model Tcl=20ns

Logic Simulators Used to simulate the output response of a logic circuit.

Logic Simulations Three primary types Circuit simulator (e.g. PSPICE)  “Exact” delay for each gate  Most accurate timing analysis  Very slow compared to other types Functional Simulation (e.g. Quartus )  Assumes one unit delay for each gate  Very fast compared to other types  Most inaccurate timing analysis Timing Simulation (e.g. Quartus)  Assumes “average” tp delay for each gate  Not the fastest or slowest timing analysis  Provides “pretty good” timing analysis

TPS Quizzes

Timing Quiz 1

Calculate all delay paths through the circuit shown below What is the shortest and longest delay?

Solution: Calculate all delay paths through the circuit shown below This circuit has multiple delay paths A-Y = 5ns+5ns+10ns=20ns B-Y = 2ns+5ns+5ns+10ns=22ns B-Y = 8ns+5ns+10ns=23ns C-Y = 8ns+5ns+10ns=23ns D-Y = 10ns Shortest path=10ns Longest path=23ns

Timing Quiz 2

Given the circuit below, find (a) Expression for the logic function (b) Longest delay in original circuit

Solution: Given the circuit below, find (a) Original logic function (b) Longest delay in original circuit Longest Delay = 7ns+7ns = 14ns

Timing Quiz 3

Given the circuit below, (a) Using Boolean Algebra, minimize the logic function (b) Longest delay in minimized circuit Delay times are NOT gates= 2ns; AND,OR gates= 5ns NAND, NOR gates= 7ns; XOR gates: 10ns XNOR gates: 12ns

Solution: Given the circuit below, find (a) Minimized logic function (b) Longest delay in minimized circuit Delay times are NOT gates= 2ns; AND,OR gates= 5ns NAND, NOR gates= 7ns; XOR gates: 10ns XNOR gates: 12ns You can show

Solution: Given the circuit below, find (a) Minimized logic function (b) Longest delay in minimized circuit Delay times are NOT gates= 2ns; AND,OR gates= 5ns NAND, NOR gates= 7ns; XOR gates: 10ns XNOR gates: 12ns Longest delay is 7ns

Solution Expanded

Given the circuit below, (a) Using a Truth Table and a K-map, minimize the logic function

Solution Do yourself!

D-FF Timing Section 6.3.3

Def : Clock Period and Switching Frequency Tc = cycle period, seconds 0 Tc Switching frequency,

D-FF Timing Parameters Timing Diagram 0Tsu= setup time D must be stable (unchanging) tsu seconds before the clock edge Thd = hold time D must be stable thd seconds after the clock edge. Tq = register delay time Q becomes valid tq seconds after the clock edge. time If Tsu or Thd are violated, data are NOT stored in D-FF

Maximum Switching Frequency How fast can our circuits operate

Maximum Switching Frequency Model W We need to find the minimum time, Tc,min, needed to propagate a signal from input X to node W. No feedback and thd=0ns

Maximum Switching Frequency Model W From the model, we see that the minimum cycle time is Register Setup time No feedback and thd=0ns

Timing Diagram Maximum Switching Frequency Tc,min This model assumes tq+tout < tin+tcl+tsu

We have a setup time violation because the clock is too fast!!! Clock is too fast!!!

Correcting a Setup Time Violation 1.Slow down the clock so that However, in most cases, Tc is a system parameter which cannot be changed. Plus, most users want their designs to go faster not slower. 2. Use a pipeline design. Let’s examine this option more closely.

Original Design W

Let’s break the F Logic into two components, so that F = F1 + F2 and tcl = tcl1 + tcl2 Pipeline Design

Now, let’s add two register blocks. One between F1 and F2 and another one at the output.

Pipeline Design Minimum Cycle Time for Each Stage Stage 1Stage 2 Stage 1Stage 2 For simplicity,

Pipeline Design Maximum Switching Frequency Calculation Stage 1Stage 2

Pipeline Design Maximum Switching Frequency Calculation where ; We have, or, so,

Pipeline Design Maximum Switching Frequency Calculation Stage 1Stage 2 In other words, the pipeline design can run 2x as fast as the original design. Let’s look at a timing diagram to see why.

Stages 1 and 2 run in parallel Too Slow

End of Lecture

N-stage Pipeline Design

Let’s extend this concept to an N stage pipe What is the maximum switching frequency? Let the total logic delay Tcl = Tcl1+Tcl2+ …. + Tcl,N

i.e. all stages have equal delays. We have for each stage:

Now, assume So Or,

In other words, the pipelined design will operate N times faster than the original design.

Now, let’s set So Or, constant

So, constant

In other words, the absolute maximum frequency of any design is fixed at We can use this formula to perform a “back of the envelope” calculation to determine if a desired switching frequency is “feasible”

The pipeline approach is a very powerful design technique. However, we have two major trade-offs using a pipelined design. They are 1.Data Load Time and 2. Data Latency Time

DATA Load Time At power-up, we must first “load” the pipeline. This will require a time of Note as, we find, unacceptable

DATA Latency Time Data will require a finite time to progress through the pipe, this is equivalent to the Data load time. Note as, we find, unacceptable