Silicon-on-Sapphire (SOS) Technology and the Link-on-Chip Design for LAr Front-end Readout Ping Gui, Jingbo Ye, Ryszard Stroynowski Department of Electrical Engineering Physics Department Southern Methodist University ATLAS Liquid Argon Colorimeter Upgrade Workshop June 23, 2006

Outline Introduction Silicon-on-Sapphire (SoS) Technology SoS Test Chip Link-on-Chip Design

Radiation-hardening-by-Design (RHBD) The wide availability of commercial IC processes has led to the philosophy of “radiation hardening by design”. Explore circuit topologies and layout techniques to create radiation-tolerant circuits Submicron bulk CMOS inexpensive BiCMOS ideal for mixed-signal design, but very expensive SOI/SOS relatively new, growing in popularity

Radiation Hardening by Design Total Dose Effect Enclosed layout Transistors Guarded ring Single Event Effect Marjory vote circuits Error detection/correction Coding Charge dissipation technique Temporal filtering technique Trade-off between radiation tolerance, performance, area and power dissipation. G. Anelli, 2000 IEEE Nuclear Science Symposium and Medical Imaging Conference Charge dissipation technique Increase gate widths in digital logic to allow nodes to recover before the next stage switches. Temporal filtering technique Increase the write time to a memory cell or data latch by adding resistance or capacitance is a simple but effective temporal filtering technique.

Radiation-hard design challenges Techniques that minimize one radiation mechanism may have little or no effect on another. Years ago, total dose concerns dominated radiation tolerant design, but they are now secondary to single event effects (SEEs). SEEs have grown in importance as feature sizes, capacitances, and operating voltages have been reduced.

IC Feature Size and Radiation Effects Tim Holman, Radiation Effects on Microelectronics Short Course 2001

Peregrine’s SOS Technology No Single-event Latch-up in SoS CMOS! Increased immunity to SEE Ideal for radiation-tolerant mixed-signal circuit design due to minimum substrate noise BULK CMOS Insulating sapphire substrate s i o 2 N channel FET P channel FET SOS Process 200 m 100 nm    0.5um process – Ft=15GHz; Fmax = 45GHz 0.25um process – Ft= 45GHz; Fmax = 100GHz 2)       NMOS Poly gate : N+ doped 3)       PMOS Poly gate : P+ doped Tox = 60A LOCOS process Peregrine’s SOS industry’s first and only commercially qualified SOS technology

Process Features Minimum substrate noise Higher level integration of RF, mixed-signal and digital circuitry. Reduced Parasitic capacitance High performance Low Power consumption Minimum crosstalk Widely used in RF and space products Transparent substrate allows for compact and simple integration with optical devices

Flipped OE devices on SoS substrate flip chip attachment UTSi integrated photo detector UTSi integrated circuitry VCSEL driver circuitry receiver circuitry quad VCSEL array quad PIN array active CMOS layer 200 um transparent sapphire substrate (UTSi) MMF ribbon fiber Flip-chip bonding of OE devices to CMOS on sapphire No wire-bonds – package performance scales to higher data rates Rugged and compact package

Peregrine Space Optical Transceiver MTP Connector Module 0.5-um SoS Single 4+4 transceiver component with variable data rates (CML interface) Minimum data rate – 10 Mbps Maximum data rate – 2.7 Gbps per channel Radiation Total Ionizing Dose: 100 kRad(Si) SEU: > 20 MeV-cm2/mg 15 year operational lifetime 125 mW per channel power consumption (dissipated to panel mount) Vibration 15.33 gRMS for 3 minutes total 15 mm height Berg MegArray PCB socket

SoS CMOS v.s. Bulk CMOS 0.25 m SoS 0.13 m Bulk CMOS Performance Up to 10 GHz Leakage Current Substrate as an insulator (1014 ohm/m at room temperature). Reduced substrate junction capacitance leads to lower leakage current. High Leakage current Power Dissipation Reduced parasitic capacitance also leads to a lower power dissipation Crosstalk Minimum crosstalk due to reduced substrate capacitance Substrate noise causes crosstalk between channels Cost $100k for wafer mask set; $1000 per wafer $800k for wafer mask set; $800 per wafer

Back-channel Leakage Current in SOS Possible Leakage path along the Si/Sapphire interface

Preliminary Radiation Test Results on 0.5-µm SoS CMOS Technology 2.5Gbps Before radiation Transceiver chip made in 0.5um SoS CMOS Technology 2.5Gbps Post-rad 100Mrad 1.6 Gbps Post-rad 100Mrad Radiation test setup at the Northeast Proton Therapy Center

Dedicated Radiation Test Chip for a 0.25-µm SOS CMOS Single NMOS and PMOS Ring Oscillators to characterize the performance and power dissipation Shift registers to characterize SEE Standard layout, edgeless layout, majority vote circuit, resistively hardened cells Digital Standard cells Current mirrors Resistors Transistor XY matrix Current mirrors/ resistors Individual Standard Cells Ring oscillators, Ring oscillators Shift registers

Transistor Test Structures NMOS and PMOS Array PMOS and NMOS with different size Different lengths to characterize back-channel leakage current Each transistor implemented in four layouts Standard, edgeless (ELT), two-finger and four-finger layout to characterize edge leakage current 10 5 Edgeless (ELT) One-finger Two-finger

SOS Rad-hard Test Chip Layout Transistors array PLL cells CMOS Ring Oscillators Shift Registers Individual gates Resistors Differential Ring Oscillator Majority vote circuitry Chip was submitted for fabrication in Oct. 2005

Link-on-Chip Architecture Flip-chip bonding PLL and clock generator REFclock encoder Laser Laser Driver serializer Parallel Data TX transmitter Module Optical data Receiver Module Parallel Data Photonic Flip-chip bonding Decoder De- serializer TIA/LA PIN REFclock Clock/Data recovery Improve performance No off-chip high speed lines Flip-chip bonding reduces capacitance and inductance Reduce power consumption No 50-Ohm transmission lines between chips

2.5-Gbps Serializer Architecture (1,5,9,13,17) 5 bit SR1 Bits 1,3,5,7,9, 11,13,15,17,19 20-bit Word Latch Mux1 (3,7,11,15,19) SR2 5 bit Serial output 20bit Latch Mux3 5 bit SR3 (2,6,10,14,18) Mux2 Ref_clk Latch (4,8,12,16,20) SR4 5 bit Latch Bits 2,4,6,8,10, 12,14,16,18,20 Shift registers Half bit clk (625MHz) Word clock (125MHz) Load clk (125MHz) Bit clk (1.25GHz) PLL & Clk generator

PLL and Clock Generator

Phase-Locked Loop Self-biasing structure [1] Phase-frequency detector Remove process technology and environmental variability, low input tracking jitter, Wide operating frequency range Phase-frequency detector with equal short duration output pulses for in-phase inputs Charge-pump with symmetric load VCO with differential buffer delay stage with symmetric loads Loop filter [1] J. G. Maneatis, “low-Jitter Process-Independent DLL and PLL Based on Self-Biased Techniques”, IEEE JSCC, Vol. 31, No. 11, Nov. 1996.

PLL Layout Vcntrl1 Vcntrl2 Charge Charge gnd vdd PFD S2D Pump1 Pump2 d i v 5 start up div4 D2S VCO Bias Gen

Serializer Layout

Serializer + PLL & Clock Generator Clk generator PLL

1.25GHz PLL Simulation Results Lock time=1.5us

Clock Generator Output @ 1.25GHz

Serializer Simulation at 2.5-Gbps

Clock generator simulation @ 1.6GHz

Serializer Simulation @ 3.2Gpbs

Conclusion Dedicated test Chip lab has been tested and fabricated Lab and radiation testing is in progress Link-on-Chip serializer and PLL & clock generator components are completed.

Acknowledgement Paulo Moreira at CERN-EP/MIC for sharing GOL link design and many useful discussions Peregrine for sharing the cost of the chip fabrication Thank You!