FPGA Calculator Core Final Presentation Chen Zukerman Liran Moskovitch Advisor : Moshe Porian Duration: semesterial December 2012

Contents Project Overview Top Architecture Micro Architecture Testability Synthesis Results Hardware Debugging Project Educational Value Project Movie Lab Demo Projecteducationalvalue Project educational value

Project Overview Hardware implementation of calculator core : Positive integers Operands: ‘+’, ’-’, ’x’, ‘^’, ‘ { ‘, ‘ } ‘ Precedence rules compatible Manually acquisition Input via Matlab GUI Result display + debugging feedback on GUI screen 0.5 חן FPGA Calculator Core FPGA Calculator Core Result

Top Architecture Implemented integrated 0.5 חן Wishbone Intercon TX PATH WNB2 WBS2 RX PATH WBM1 WBS1 CALC_CORE WBS3 WBM3 Altera Cyclone II FPGA GUI - MATLAB Uart Out bits/sec Uart In bits/sec Clock & Reset Clock & Reset FPGA Clock, 50[MHZ] FPGA Reset Sys_clk, 100[MHZ] Sys_reset

Wishbone Intercon TX PATH WNB2 WBS2 RX PATH WBM1 WBS1 CALC_CORE WBS3 WBM3 Altera Cyclone II FPGA GUI - MATLAB Uart In bits/sec Uart Out bits/sec Implemented integrated Postfix Data. FF Postfix Data. FF Infix - Data. FF Infix - Data. FF Result Type Address Data Length Result Type Address Data Length Result SOF Type Address Data Length CRC EOF Data Flow 1.5 חן Clock & Reset Clock & Reset FPGA Clock, 50[MHZ] FPGA Reset Sys_clk, 100[MHZ] Sys_reset SOF Type Address Data Length Postfix Data. FF Postfix Data. FF CRC EOF Infix - Data. FF Infix - Data. FF

Micro Architecture 0.5 חן

Calculator Core in action detailed view A A A FF 0A A 5A FF 5A 00 5A A 1.5 חן

Testability Top Level Testing and simulating environment : Goals : 1.functionality verification (in system boundaries) 2.verification that hardware and software calculation results are equal 0.5 חן Multi-Level testing environments were implemented PLL BYPASS

PLL Vs. PLL Bypass The top level contains PLL unit that produces system clock Simulating The top level with PLL unit is slow PLL BYPASS  Disables PLL unit and produce system clock manually  Implemented one hierarchy above the PLL unit in order to get faster simulation time (if … generate)  Choosing between PLL and PLL BYPASS is done by generic sim_clk_gen_g (if true – PLL is disabled, otherwise enabled) 1.5 חן

GUI Method select Enter the exercise Exhibit the data to transmit Exercise display Software result Hardware result Gui messages 0.5 לירן

GUI - Capabilities 1 לירן Operational features: Receive data from the user Data abstraction – easy and simple operation Generates only correct packets with legal values Method choosing. Debug features: Transferred data display Messages display Generates text files available for simulation

Operation Table Select valueHex codeBinary codeOperation ( ) ^ x FF End of Postfix\infix 0.5 לירן

Text Files Calculation string txt file format : General comment – desired test literally, explanation, Clarifications etc. Different notations comment: infix, postfix, postfix in hex + operator conversion Data line - full packet calculation string Postfix data Infix data End of postfix Wishbone signals TGA – Client TypeTGD – data length ADR – Client inner address SOFCRCEnd of infixEOF General comment – desired test literally, explanation, Clarifications etc. Result string txt file format : Comment : infix notation + result [hex] Data line – full packet expected result string Wishbone signals Expected result SOFEOFCRC 0.5 חן

TextFile Text File Calculation string txt file example (4 strings): 0.5 חן

String generator + checker Allows simple & fast testing and simulation Automatic feedback – message in the transcript window Working with multiple strings one after the other 0.5 חן

String generator + checker example 1 חן Full packet calculation string Full packet result string String Generator opens the input txt file String Generator closes the input txt file End of successful top level test String Generator and Checker simulation reports – Transcript Window

Power basic tests:Adder basic tests: Multiplier basic tests: Subtractor basic tests: Test Plan Blocks Basic Tests (inputs/outputs limits and special cases): General Tests (inputs/outputs limits and special cases):  Simple string using each operator once  Strings using same operator all along  Strings using different operator in the beginning of the string  Each operator used twice in a single string  Short string  Long string  Brackets testing (in different location along the string)  Bigger\Smaller Right\Left Operand For simulation and hardware as well 1.5 לירן

Synthesis Results 0.5 חן

Max Frequency Required frequency : 100 [MHz] Actual Max frequency : [MHz] 0.5 חן

Hardware Debugging Problem : first programming on FPGA … nothing happens (GUI does not receive the returned full packet result string). Source : The reset button on the DE2 board is active low while the PLL reset polarity (predefined by the MegaWizard) is active high. Solution : adding the pll_reset signal which insures, that when the FPGA reset button is active ('0'), the PLL reset would be active as well with the appropriate polarity ('1'). Conclusion : Fundamental principle - system synthesis MUST come only AFTER successful simulation - Early detection of the problem. MegaWizard PLL RESET (areset) is always active high ('1'). Special attention should be paid to the reset polarity issue. Programming indication led could be useful. 1.5 חן

Planning and Specifying a Project Writing reusable generic code Profound acquaintance with communication protocols : UART, Wishbone Integration of many components Verifying logic correctness using smart simulators, waveforms, text files and scripts (do files) Using the GUI for hardware Testing and also as a producer of text files which are used later by the smart simulators Documentation of the work done SVN is a very useful tool Seriousness, Persistence, spending time and a will to learn and understand are a Guarantee of success Project Educational Value 1.5 חן

Project Movie

Lab Demo