CMOS Activities K. Arndt, D. Bortoletto, T. Huffman, J.J. John, K. Kanisauskas, R. Nickerson, R. Plackett, L. Vigani With many thanks to V. Fadeyev (SCIPP.

Slides:



Advertisements
Similar presentations
HV/HR-CMOS sensors (A quick overview from personal perspective, which is biased on ATLAS strips work) V. Fadeyev SCIPP / UCSC SiD mtg at SLAC,
Advertisements

H1 SILICON DETECTORS PRESENT STATUS By Wolfgang Lange, DESY Zeuthen.
The ATLAS Pixel Detector
ATLAS SCT Endcap Detector Modules Lutz Feld University of Freiburg for the ATLAS SCT Collaboration Vertex m.
ATLAS Module building at Glasgow
Development of an Active Pixel Sensor Vertex Detector H. Matis, F. Bieser, G. Rai, F. Retiere, S. Wurzel, H. Wieman, E. Yamamato, LBNL S. Kleinfelder,
Workshop on Silicon Detector Systems, April at GSI Darmstadt 1 STAR silicon tracking detectors SVT and SSD.
Chip Developments of the Bonn Group Hans Krüger, Bonn University -1-
Studies and status of CMOS-based sensors research and development for ATLAS strip detector upgrade 1 Vitaliy Fadeyev, Zach Galloway, Herve Grabas, Alexander.
Victoria04 R. Frey1 Silicon/Tungsten ECal Status and Progress Ray Frey University of Oregon Victoria ALCPG Workshop July 29, 2004 Overview Current R&D.
Embedded Pitch Adapters a high-yield interconnection solution for strip sensors M. Ullán, C. Fleta, X. Fernández-Tejero, V. Benítez CNM (Barcelona)
Ivan Peric, WIT Active Pixel Sensors in high-voltage CMOS technologies for ATLAS Ivan Perić University of Heidelberg, Germany.
A multi-chip board for X-ray imaging in build-up technology Alessandro Fornaini, NIKHEF, Amsterdam 4 th International Workshop on Radiation Imaging Detectors.
March 20, 2001M. Garcia-Sciveres - US ATLAS DOE/NSF Review1 M. Garcia-Sciveres LBNL & Module Assembly & Module Assembly WBS Hybrids Hybrids WBS.
U.S. ATLAS Executive Meeting Upgrade R&D August 3, 2005Toronto, Canada A. Seiden UC Santa Cruz.
Monolithic Pixels R&D at LBNL Devis Contarato Lawrence Berkeley National Laboratory International Linear Collider Workshop, LCWS 2007 DESY Hamburg, May.
Semi-conductor Detectors HEP and Accelerators Geoffrey Taylor ARC Centre for Particle Physics at the Terascale (CoEPP) The University of Melbourne.
Annual Meeting WP2- Sensors Heinz Pernegger / CERN 20 November 2013.
RD50 participation in HV-CMOS submissions G. Casse University of Liverpool V. Fadeyev Santa Cruz Institute for Particle Physics Santa Cruz, USA HV-CMOS.
SLHC SG: ATLAS Pixel G. Darbo - INFN / Genova SLHC SG, July 2004 ATLAS Pixel at SLHC G. Darbo - INFN / Genova Talk overview: A table with different High.
Status of the MaPMT o Status quo o Ongoing work o Issues – mechanics – electronics – schedule o Conclusions LHCb meeting Milano Franz Muheim.
Fully depleted MAPS: Pegasus and MIMOSA 33 Maciej Kachel, Wojciech Duliński PICSEL group, IPHC Strasbourg 1 For low energy X-ray applications.
Foundry Characteristics
ASIC R&D at Fermilab R. Yarema October 30, Long Range Planning Committee2 ASICs are Critical to Most Detector Systems SVX4 – CDF & DO VLPC readout.
ATLAS PIXEL SYSTEM OVERVIEW M. Gilchriese Lawrence Berkeley National Laboratory March 11, 1999.
Thin Silicon R&D for LC applications D. Bortoletto Purdue University Status report Hybrid Pixel Detectors for LC.
AMS HVCMOS status Raimon Casanova Mohr 14/05/2015.
Valerio Re, Massimo Manghisoni Università di Bergamo and INFN, Pavia, Italy Jim Hoff, Abderrezak Mekkaoui, Raymond Yarema Fermi National Accelerator Laboratory.
Technology Overview or Challenges of Future High Energy Particle Detection Tomasz Hemperek
UK Activities on pixels. Adrian Bevan 1, Jamie Crooks 2, Andrew Lintern 2, Andy Nichols 2, Marcel Stanitzki 2, Renato Turchetta 2, Fergus Wilson 2. 1 Queen.
BTeV Hybrid Pixels David Christian Fermilab July 10, 2006.
10th Trento Workshop on Radiation Detectors HVCMOS Sensors for LHC Upgrade Felix Michael Ehrler, Robert Eber Daniel Münstermann, Branislav Ristic, Mathieu.
Irfu saclay Development of fast and high precision CMOS pixel sensors for an ILC vertex detector Christine Hu-Guo (IPHC) on behalf of IPHC (Strasbourg)
The development of the readout ASIC for the pair-monitor with SOI technology ~irradiation test~ Yutaro Sato Tohoku Univ. 29 th Mar  Introduction.
Radiation hardness of Monolithic Active Pixel Sensors (MAPS)
HV-HR CMOS activity in Glasgow TCAD simulations of TowerJazz HR-CMOS sensors Characterisation of AMS350nm HV-CMOS pixels & strips R. Bates, C. Buttar,
LHCb Vertex Detector and Beetle Chip
W. Kucewicz a, A. A.Bulgheroni b, M. Caccia b, P. Grabiec c, J. Marczewski c, H.Niemiec a a AGH-Univ. of Science and Technology, Al. Mickiewicza 30,
CMOS Sensors WP1-3 PPRP meeting 29 Oct 2008, Armagh.
WG3 – STRIP R&D ITS - COMSATS P. Riedler, G. Contin, A. Rivetti – WG3 conveners.
UK Bump Bonding (Flip-chip) Meeting at Daresbury (15th May): Tentative Agenda 10:00 Coffee Introduction and Welcome: Phil Allport (Liverpool) 10:40.
PHENIX Vertex Detector with Conventional Strip Sensors Abhay Deshpande Stony Brook University.
MIMO  3 Preliminary Test Results. MIMOSTAR 2 16/05/2007 MimoStar3 Status Evaluation of MimoStar2 chip  Test in Laboratory.
Ideas for Super LHC tracking upgrades 3/11/04 Marc Weber We have been thinking and meeting to discuss SLHC tracking R&D for a while… Agenda  Introduction:
Progress with GaAs Pixel Detectors K.M.Smith University of Glasgow Acknowledgements: RD8 & RD19 (CERN Detector R.&D. collaboration) XIMAGE (Aixtron, I.M.C.,
SuperKEKB 3nd open meeting July 7-9, 2009 Hans-Günther Moser MPI für Physik Sensor and ASIC R&D Sensor Prototype Production: running, ASICs: Switcher,
Status of Stripixel Sensor + SVX4 Test Junji Tojo RIKEN VTX Meeting June 1 st, 2004.
RD program on hybrids & Interconnects Background & motivation At sLHC the luminosity will increase by a factor 10 The physics requirement on the tracker.
News on Mechanical Design Dirk Wiedner July /4/20121Dirk Wiedner Mu3e meeting Zurich.
Ideas on MAPS design for ATLAS ITk. HV-MAPS challenges Fast signal Good signal over noise ratio (S/N). Radiation tolerance (various fluences) Resolution.
Hybrid CMOS strip detectors J. Dopke for the ATLAS strip CMOS group UK community meeting on CMOS sensors for particle tracking , Cosenors House,
Low Mass, Radiation Hard Vertex Detectors R. Lipton, Fermilab Future experiments will require pixelated vertex detectors with radiation hardness superior.
TCT measurements of HV-CMOS test structures irradiated with neutrons I. Mandić 1, G. Kramberger 1, V. Cindro 1, A. Gorišek 1, B. Hiti 1, M. Mikuž 1,2,
Update on & SVT readout chip requirements
Dima Maneuski, Advances in rad-hard MAPS 2016, Birmingham
Ivan Peric, Christian Kreidl, Peter Fischer University of Heidelberg
HV/HR CMOS in Oxford: Facilities, experience, and interests Arndt, Bortoletto, Huffman, Jaya John, Nickerson, Placket, Shipsey, Vigani.
Introduction HV HR CMOS ATLAS R&D
SVT – SuperB Workshop – SLAC 6-9 Oct 2009
ATLAS strip CMOS Development of Sensors for possible use in Silicon Strip region at phase II Aggressive time schedule – drives choices Three phase programme.
Silicon Pixel Detector for the PHENIX experiment at the BNL RHIC
HR-HV CMOS activities and plans at Glasgow
HV-MAPS Designs and Results I
HV-CMOS Update The properties device (HVStripV1) we just Birmingham
HVCMOS sensor technology R&D
Ivan Peric for ATLAS and CLIC HVCMOS R&D and Mu3e Collaborations
HR CHESS News Jens (et. al.).
ASICs and Sensors Hybrid systems Helmholtz Program: Matter
HVCMOS Detectors – Overview
Presentation transcript:

CMOS Activities K. Arndt, D. Bortoletto, T. Huffman, J.J. John, K. Kanisauskas, R. Nickerson, R. Plackett, L. Vigani With many thanks to V. Fadeyev (SCIPP / UCSC) who provided most of these slides Oxford ATLAS upgrades overview, CMOS Activities1

Outline o Baseline ATLAS strips o Why consider CMOS o What is HV/HR CMOS o Technology choices and options o Oxford hardware development and testing o Next steps 2Oxford ATLAS upgrades overview, CMOS Activities

Baseline ATLAS Strip Tracker 3 From I. McGregor’s IDR presentation The tracker (~200 m 2 ) is composed of barrels/endcaps. Which are composed of staves/petals. Which are composed of modules. These objects have been prototyped over last >= 3 years by multiple groups. There are no serious technical problems. V. Fadeyev Oxford ATLAS upgrades overview, CMOS Activities

Baseline ATLAS Strip Module 4 A barrel module from last round of prototyping (with ABCN-250 chips). Traditional heterogeneous architecture: Separate sensors and readout ASICs. Differences with current ATLAS SCT modules: n-on-p sensor as more rad-hard Single-sided module Single large sensor Direct gluing of hybrid on sensor More channels/module (and more modules in production) Next round of prototyping is imminent. It features new ASICs, ABC-130, with x2 channels/chip => half the chips and less hybrid area/material. 10x10 cm 2 sensor with 5120 channels; 40 ABCN-250 chips on 2 hybrids V. Fadeyev Oxford ATLAS upgrades overview, CMOS Activities

Why consider CMOS? Recent successes with CMOS in studies for the Pixel upgrades raised the question of whether CMOS could be applied to the Strip upgrades. Possible improvements compared to the baseline: o Cost savings due to x2 less area and less cost per area -- higher-volume processes o Faster construction due to fewer wirebonds. o Less material in the tracker. Work Plan ATLAS agreed to explore the possible use of the technology, with 3-year plan: o Year 1: Characterization of basic sensor/electronics properties and architecture <<<<< we are here o Year 2: Fabricating and evaluating a large-scale device. o Year 3: Full prototypes of sensors and ABCN’. There is a review of progress at the end of each year (breakpoint). 5 V. Fadeyev Oxford ATLAS upgrades overview, CMOS Activities

What is HV/HR-CMOS High-Voltage CMOS technology is a variation of standard CMOS process that is frequently used for power devices. Allows for higher-resistivity substrates and ~100 V bias. High-Resistivity CMOS was developed for imaging applications. Features high- resistivity thin epi layers one can take advantage of. Bottom line: higher V(bias) and  than for commercial CMOS, although not as high as for what HEP is used to. 6 V. Fadeyev

Projects within ATLAS There are two projects within ATLAS evaluating HV/HR CMOS technologies: o Pixel demonstrator project o Evaluation for strip sensor But there are also other possibilities being pursued to some extent: o Additional outermost pixel layers o Muon high-eta extension 7 V. Fadeyev

CMOS Strips Introduction A CMOS chip could detect hits and process them digitally, combining the functions of sensors and readout chips on a single piece of silicon. In practice, we don’t have enough time for such a complex development. We need to start sensor pre- pre-production in 3 years. This lead to a very focused programme: o A working group was formed that outlined most promising use of the technology as sensor replacement: o Could still have amplifiers and comparators on chip, but the rest of digital processing, command I/O, trigger pipelines, etc will go into (modified) ABCN – preserving the rest of the readout chain. o Transmitting high-speed information instead of individual analog signals to readout ASICs. o Even though this is a strip system, the active area is pixelated, with connections to the periphery that result in longitudinal information. o Looking at ~40  m pitch and 800  m length of pixel region (better than 74.5 um baseline pitch and 40 mrad crossing angle). o Max reticle sizes are ~2x2 cm 2 => Looking into rows of 4-5 chips as basic units (yield performance is critical here). o This would take advantage of the rest of the mechanical/cooling/readout/power architecture of staves that was developed for the baseline program over past several years. o R&D with two foundries is being pursued: AMS and TJ. (Pixel efforts have more, e.g. L-foundry.) 8 V. Fadeyev

First Year Efforts The goal of 1 st year work is to understand the properties of signal (radiation tolerance, timing resolution, power, noise), pixel layout, and on-sensor readout architecture. Had 3 chip submissions to figure out basic sensor properties: o HVStripV1 by Ivan Peric (Karlsruhe/KIT) o CHESS-AMS by H. Grabas et al (UCSC), A. Dragone et al (SLAC) o CHESS-TJ by R. Turchetta et al (RAL) There is a pending AMS architectural submission (SLAC/UCSC/Ivan Peric), to be submitted in March. 9 Transistors, amplifiers, passive pixel arrays, active pixel arrays V. Fadeyev Oxford ATLAS upgrades overview, CMOS Activities

Oxford hardware development We develop boards used to evaluate the CMOS test chips: So far: HVStripV1 daughterboard (T. Huffman, JJ John, M. Jones) HVStripV1 motherboard (K. Foster, T. Huffman, JJ John) Currently developing: (with input from DESY, RAL, UCSC and SLAC) CHESS motherboard CHESS-AMS daughterboard CHESS-TJ daughterboards x 2 chip flavours 10Oxford ATLAS upgrades overview, CMOS Activities

X-rays test beam at Diamond Light Source: Oxford HVStripV1 Testing (working closely with DESY, Glasgow and RAL) 11 Glasgow/Oxford/RAL/DESY Oxford ATLAS upgrades overview, CMOS Activities Scan across pixel dimensions: 40x400 µm Hitting just one pixel Scan of all pixels

Fe-55 peak example HVStripV1 Tests (continued) 12 K. Kanisauskas, R. Plackett, L. Vigani Oxford ATLAS upgrades overview, CMOS Activities Gain map – analogue injection Bias sweep MOSFET characterisation

Upcoming work Currently:detailed characterisation of 3 HVStripV1 chips with Glasgow and RAL In parallel:design of CHESS hardware End of Jan: proton irradiation of 2 of these at Birmingham Feb:detailed characterisation, post-irradiation Mid-March:electron test beam at DESY design boards for architectural chip submissions Generally: develop hardware and irradiate and characterise test chips towards the programme milestones. 13Oxford ATLAS upgrades overview, CMOS Activities

Reference Information Not meant to be exhaustive, but rather to give leads to several efforts/foundry trials: AMS: Peric et al, “High-voltage pixel detectors in commercial CMOS technologies for ATLAS, CLIC and Mu3e experiments”, NIM A 731 (2013) 131 TowerJazz: J. Crooks et al, “Kirana: a solid-state megapixel uCMOS image sensor for ultra-high speed imaging”, Proc. SPIE 8659, Sensors, Cameras, and Systems for Industrial and Scientific Applications XIV EPC: M. Havranek, T. Hemperek, et al, “DMAPS: a fully depleted monolithic active pixel sensor - analog performance characterization”, XFAB: T. Hemperek et al, “A Monolithic active pixel sensor for ionizing radiation using a 180nm HV-SOI process”, Workshop on Active Pixel Sensors for Particle Tracking (CPIX14), Bonn, September 2014, 14 V. Fadeyev Oxford ATLAS upgrades overview, CMOS Activities