Implementing and Optimizing a Direct Digital Frequency Synthesizer on FPGA Jung Seob LEE Xiangning YANG

Direct Digital Frequency Synthesizer (DDFS) Generate sinusoid and cosinusoid waveform Widely used in digital communication system – Software radio – Spread-spectrum modulation – Phase shift-keying modulation

DFFS Algorithm Look-up table – Fast, less sophisticated design, high precision – Huge table == large area, inflexible Angle rotation: CORDIC, interpolation, etc. – Compact, area efficient, flexible – Complex design, low speed, wide internal data- path to ensure desired output precision

DFFS Algorithm Used in our project: hybrid method – Use LUT to gives a coarse position of the angle – Use angle rotation method to fine turn the angle Engineering trade-off of area efficiency, design complexity, computation need, and cycle times 16-bit internal data path to give 15 bit output precision 2 128x16-bit LUTs are needed – [Lee & Park] S. Lee and I. Park, “Quadrature direct digital synthesis using fine-grain angle rotation”, ISCAS’2004

Implementation Implementing the algorithm on FPGA with algorithm mapping and transforming approach – Non-pipeline Optimizing – cut-set retiming techniques => pipeline version

FPGA Implementation Choose Altera Cyclone II EP2C5 – Low cost FPGA, – On-line listed price: $12.8 – Internal RAM for LUT

Current Status A software implementation of the algorithm – For studying the characteristics of the algorithm Non-pipeline version is finished – Test bench – it works! – Synthesis: max sample output frequency (max operating frequency) : MHz

Next Stage Implementing the pipe-line version Further optimization: – Parallel processing ? – Buffering ?

Thank You Question ?

Pipelined Retiming Add registers to 3 stages: 2 stage -> 6 stage pipelined structure

Comparison between retiming and non-retiming version Maximum Clock rate – Non-pipelined version: 42.84MHz – Pipelined version: 116 MHz Critical path delay is reduced as much as 2.7 times Total cell Area change? – Non-pipelined version: – Pipelined version: