May 2007Pixel Electronics --- US ATLAS Upgrade R&D --- Garcia-Sciveres1 Pixel Electronics slides for UCSC Cover 0.13 FE chip ROD Other Activities (except DC-DC)

May 2007Pixel Electronics --- US ATLAS Upgrade R&D --- Garcia-Sciveres2 Progress in FY07 Epilogue from 2004 test chip Preamp chip submission & testing Workshop at CERN Work-plan for full size chip submission –Includes non-US manpower CPPM: Bonn: Genova: –US to focus on unique capabilities Analog design Architecture Full chip integration

May 2007Pixel Electronics --- US ATLAS Upgrade R&D --- Garcia-Sciveres test chip epilogue CPPM has prepared an SEU measurement setup using the LBNL um test chip. They are irradiating with 20GeV protons at CERN right now to extend the studies done at the LBNL 88” cyclotron in FY06. LBNL simply provided test boards, a few chips, and advice, but we are getting a great deal in return More on collaboration with European institutes later…

May 2007Pixel Electronics --- US ATLAS Upgrade R&D --- Garcia-Sciveres4 Analog test chip submitted Feb nm bulk CMOS 840 pixels complete with threshold and bias registers. 2 basic charge-integrating amplifier designs: –resistor continuous reset. –current source continuous reset. nominal current 22  A/pixel –Goal for final chip is ~10  A/pixel Simulated ENC ~200e- for 400fF input load and ~20ns peaking time –Exact value depends on many tunable parameters 2.8mm 3.6mm

May 2007Pixel Electronics --- US ATLAS Upgrade R&D --- Garcia-Sciveres5 Analog test chip plans Expected chip delivery late May Test board in fabrication now Initial “checkout” by Abder at LBNL Distribution of chips to other test efforts in June/July –Interest from European collaborators to participate in testing Some irradiation possible in FY07, but mainly in 08 –Hope that European colleagues will set up irradiation tests in FY08- no project fund request for this. –Note that all transistors are linear (with guard rings around Nmos) Critical initial measurements expected –Threshold dispersion –Uniformity across array. Operating margin. –Current consumption, noise and timewalk

May 2007Pixel Electronics --- US ATLAS Upgrade R&D --- Garcia-Sciveres6 Pixel Upgrade Electronics Workshop Held on March 22 at CERN following ATLAS-CMS Electronics (ACES) workshop electical engineers not presently involved in pixels attended this meeting –CPPM, Bonn, Nikef, Genova –Clearly there is interest Work Plan drafted in April to foster efficient collaboration –First global chip designers’ pone meeting to go over this plan isnext week

May 2007Pixel Electronics --- US ATLAS Upgrade R&D --- Garcia-Sciveres7 Plans for FY08 Work-plan milestones –Architecture definition: September 2007 –Initial Design review: January 2008 –Final Design review: September 2008 –First full size chip submission: December 2008 LBNL engineering manpower –100% Abder Mekkaoui: Lead IC designer, analog front end, integration –40% Dario Gnani: IC designer, High level description, readout logic –30% George Chao: Pad frame –10% Peter Denes: Organization, pads. (no cost to project) LBNL purchases/fabrications –Assume a second iteration of front end design (if nothing else to fine tune lower current modifications): $65K including test board.

May 2007Pixel Electronics --- US ATLAS Upgrade R&D --- Garcia-Sciveres8 FY09 Continue same level of design effort until submission –For Dec. submission this is 25% of FY08 manpower cost Reduced effort still needed after submission in FY09 for simulation and testing –Take 50% of FY08 cost for remaining 75% of FY09 Finally need to cover test board design (based on existing TPLL) and fabrication –EE, drafter, and board fab cost. –Student-like personnel to operate test setup Cost of engineering run to be paid out of BL replacement ATLAS project, which is M&O-B with the usual sharing. –20% of $400K

May 2007Pixel Electronics --- US ATLAS Upgrade R&D --- Garcia-Sciveres9 LBNL FE chip Cost breakdown FY08-09

May 2007Pixel Electronics --- US ATLAS Upgrade R&D --- Garcia-Sciveres10 Chip Requirements Pixel size50 x 250 m2m2 Bump pad diameter12 mm InputDC-coupled negative polarity Normal pixel input capacitance range* fF Long pixel input capacitance range* fF In-time threshold with 20ns gate4000e Two-hit time resolution400ns DC leakage current tolerance100nA Single channel ENC sigma (400fF)300e Tuned threshold dispersion100e Analog supply AA Radiation tolerance200MRad Average hit rate200MHz/cm 2 Acquisition modeData driven with time stamp Time stamp precision8bits Readout initiationTrigger command Max. number of continuous triggers16 Trigger latency3.2 ss Single chip data output rate160Mb/s * Low value given by planar sensors and high value by 3D. Very difficult. Critical for power distribution and material High luminosity and small radius. Wants new ROD

May 2007Pixel Electronics --- US ATLAS Upgrade R&D --- Garcia-Sciveres11 ROD development ROD total bandwidth limited by output s-Link at 1.28Gb/s. This is only enough for 8 chips at 160Mb/s each. This would have to fed into the ROD on 32 40Mb/s inputs. To read out a single R=4cm layer would need 94 RODs! It would be much cheaper and reliable to build fewer new, faster RODs using modern components Can keep the basic data flow architecture, but simply implement within new FPGA. This is NOT yet an urgent need. Could in principle start in FY09 instead of FY08, but –There is available manpower in FY08 –Early design would feed-back into chip I/O architecture, leading to a better system –There is synergy with PLL-based test setup needs

May 2007Pixel Electronics --- US ATLAS Upgrade R&D --- Garcia-Sciveres12 ROD & PLL test setup Interface definition is common to ROD and PLL test setup work, and is needed for chip architecture design. Expertise at LBNL is common to ROD and PLL test setup (same people) FY08 Tasks to be covered in the ROD/PLL area are: –Interface definition –Schematic layout of revised PLL test card –Initial look at new generation candidate FPGA for replacement ROD. FY08 requested resources (split between chip and ROD) –0.2 FTE under –0.083 FTE under ROD –10K M&S under ROD (Xilinix evaluation boards) FY09 requested resources (split between chip and ROD) –0.53 FTE under (includes PLL test card layout & fab) –0.3 FTE under ROD (prototype BOC and ROD design) –30K M&S under (PLL test card fab)

May 2007Pixel Electronics --- US ATLAS Upgrade R&D --- Garcia-Sciveres13 LBNL ROD Cost breakdown FY08-09

May 2007Pixel Electronics --- US ATLAS Upgrade R&D --- Garcia-Sciveres14 Other LBNL activities Progress in FY07 in –3D sensor testing and –Nanowire carpet hybrid pixel development 3D sensor testing –Minor involvement but very positive impact Established characterization setup at CERN enabling test work by U. of Oslo Provided test boards and debugging help Results from this work used to specify load requirement on new 130nm amplifier. –Will need to increase involvement in FY09 once first 130nm full chip is available Note request for “tester” support in FY

May 2007Pixel Electronics --- US ATLAS Upgrade R&D --- Garcia-Sciveres15 Nanowire carpet hybrid pixels W. Kim (molecular foundry), C. Tindall (eng.), H. Spieler (phys.), M. Garcia-Sciveres (phys.), and brand new addition CERN Medipix group 2007 Realized implementation Concept shown at UCSC upgrade meeting Nov. 2005

May 2007Pixel Electronics --- US ATLAS Upgrade R&D --- Garcia-Sciveres16 Nanowire carpet hybrid pixels (cont.) Funding sources so far –LBNL molecular foundry (FY06) –LBNL LDRD “surplus” (FY06) –ATLAS project R&D 0.07FTE (FY07) –No explicit ATLAS R&D request for FY08 Diode behavior of NW carpet sample fabricated by C. Tindall in FY07