® /1 The E is the Edge

® /2 Density Leadership Virtex XCV1000 Density (system gates) 10M Gates In 2002 Virtex-E XCV3200E Virtex™ Architecture Extends to 10 Million System Gates 4M 3M 1M 10M Virtex-II

® /3 Process Leadership Courtesy and Copyright of UMC 0.18 micron process Three Million System Gates Twice the nearest competitor 73,008 Logic Cells 1.3x the nearest competitor 832 Kbits Internal Block RAM Twice the nearest competitor 210 Million transistors First in the programmable industry 0.15 micron L eff Six Metal Layers Massive Segmented Routing predictably fast designs

® /4 The Virtex Success Fastest ramping FPGA family in industry 4x previous ramp De facto standard for FPGAs

® /5 2.1i Software Support for 2M gates Internet Team Design Complete EDA support CLB IOB BRAMBRAM DLL BRAMBRAM CL CLB IOB CLB IOB IOBIOB IOBIOB DLL CL IOB DLL IOB BRAMBRAM CLB BRAMBRAM IOBIOB IOBIOB BRAMBRAM BRAMBRAM IOBIOB IOBIOB BRAMBRAM DLL CLB IOB CLB IOB CLB IOB CLB BRAMBRAM DLL IOBIOB CL IOBIOB DLL IOB IOBIOB BRAMBRAM BRAMBRAM CLB IOBIOB IOBIOB BRAMBRAM BRAMBRAM IOBIOB... Differential I/O 622 Mbps LVDS LVPECL Bus LVDS 311+ MHz performance 8 DLLs in every device Deskew 4 system Clks Zero-delay clock conversion More Block RAM Up to 832Kbits 250 MHz CLKIN CLKFB RST CLK0 CLK90 CLK180 CLK270 CLK2X CLKDV LOCKED Port A Dual-Port 4Kbit BRAM Port B New in Virtex-E

® /6 Building on Virtex Success  >3x the density - 1M to >3M System Gates  1.3x in internal logic performance MHz  >1.5x in I/O count I/Os to 804 I/Os  >3x in I/O performance Mbps to 622 Mbps  6.5x in BlockRAM Kbits to 832 Kbits  2x in number of DLLs - 8 over 311MHz  Baseline features/functionality of Virtex  Design compatible with Virtex  Industry leading price points The Best Just Got Better!

® /7 Terabit Memory Continuum bytes kilobytes megabytes Virtex On-Chip SelectRAM+ TM Memory 16x1 4Kx1 2Kx2 1Kx4 512x8 256x16 DSP Coefficients Small FIFOs Shallow/Wide Large FIFOs Packet Buffers Video Line Buffers Cache Tag Memory Deep/Wide SDRAM ZBT SSRAM SGRAM DDR QDR 3 Level Memory Hierarchy Enables Terabit Bandwidth Highest performance FPGA memory system Distributed RAMBlock RAMExternal RAM

® /8 Logic Cell & Memory Leadership XCV ,648 LCs 128 Kbit BRAM XCV3200E 73,008 LCs 832 Kbit BRAM Virtex-E with 10% Logic Cells used as RAM

® /9 Virtex-E Supports 20 I/O Standards SDRAM SSTL GTL+ LVCMOS HSTL SRAM HSTL, LVDS Chip to Chip LVTTL, LVCMOS2, LVCMOS18, 5V* LVDS, LVPECL *With external resistor Chip to Memory SSTL2-I, SSTL2-II, SSTL3-I, SSTL3-II, HSTL-I, HSTL-III, HSTL-IV, CTT Chip to Backplane PCI66_3V, PCI33-3V, GTL, GTL+, AGP2X, Bus LVDS Future SelectI/O+ Technology allows support for future standards Select I/O+ TM Technology Any standard on any pin Multiple standards simultaneously BLVDS LVTTL

® /10 No Bottleneck I/O Bandwidth Unparalleled Flexibility  SelectI/O+™ Technology —Interfaces to 20 I/O standards including: – Bus LVDS, LVDS & LVPECL —344 differential pairs or 804 single-ended I/Os —Any I/O to Any standard —622 Mbps differential I/Os —>311 Mbps single-ended I/Os  SelectI/O+™ Technology —Interfaces to 20 I/O standards including: – Bus LVDS, LVDS & LVPECL —344 differential pairs or 804 single-ended I/Os —Any I/O to Any standard —622 Mbps differential I/Os —>311 Mbps single-ended I/Os Over 100 Gbps aggregate bandwidth supporting multiple 10 Gbps ports Block 2 Block 3 Block 4 Block 5 Block 6 Block 7 Block 0 Block 1 External Port (512x64) Internal Port (256x128) DLL 78MHz 128 bits BLVDS 311 Mbps per pair 32 pairs in 32 pairs out DLL BLVDS 155 MHz Clocks forwarded with data CLB 1:2 mux demux 155MHz 64 bits 311 MHz155 MHz78 MHz 2X XX/2

® /11 I/O Leadership 804 I/Os 512 I/Os 344 I/O Pairs

® /12 High Performance Clocking Solution Receive and convert high speed clocks (over 100MHz) with zero delay Zero-Delay Local Clock Generation to Any of Virtex-E I/O Standards Virtex-E Eliminates PECL-to-TTL Converters -- Eliminates 2ns Delay & Skew Device LVPECL Clock Source LVPECL Clock Distributor Virtex-E n Virtex-E 2 2 Example Devices: Motorola MC10/100E111 Synergy SY10E111LE Virtex-E No LVPECL-TTL Translator Two Equal-Length Point-to-Point LVPECL PCB Clock Traces TTL SSTL DLL Virtex-E 1

® /13 Full Deskew of 4 Clocks DLL Clk-1 Clk-2 Clk-3 Clk-4 Clk-1 Clk-2 Clk-3 Clk-4 Clk-1 Clk-2 Clk-3 Clk-4 Zero Delay External Clocks Zero Delay Internal Clocks Each Clock can be Multiplied/Divided -- External Clocks can be I/O Translated

® /14 Complete S/W and IP Support  High performance S/W tools : Xilinx 2.1i S/W — Two million gate design capability — Further compile time reduction of 50% — Internet Team Design (Xilinx iTD™) tool — Complete EDA vendor support — EDA vendor design tools to further enhance signal integrity and noise immunity  Complete IP support — CORE Generator™ 2.1i — Popular BaseBLOX™ cores and reference designs available — Real-PCI™ 64/66 and 32/33 PCI solutions available

® /15 Packaging Leadership Footprint compatible with Virtex family- CS144, BG432/560, FG256/456/676/680 Offers both low-cost and high thermal dissipation packages Max user I/O is lesser of the max I/O and max device I/O Max user I/O is lesser of the max I/O and max device I/O  Devices Available Now   

® /16 Virtex-E Solution  Building on The Most Successful FPGA Series  The Most Flexible System Level Integration Solution — First to deliver complete differential support including LVPECL, BLVDS, and LVDS  Highest I/O Bandwidth — Over 100 Gbps aggregate bandwidth — Ideal for data communication and DSP applications  Highest Memory Bandwidth — Internal terabit bandwidth — True Dual-Port™ capability — Direct interface to high performance memories  Packaging Leadership in Offering and Reliability  Complete Design Tool and IP support  Industry Leading Price Points

® /17 Industry Leading Price Points XCV100E$16.50$13.20 XCV300E$41.20$32.90 XCV1000E$276.00$ XCV2000E$582.00$ * Note: Denotes 100Ku Resale Pricing End 00*End 01*