AMCOM M261/MK66

AMCOM M261/Mk66 missile: Fall Review 2 Matt Galante Adrian Lauf Ashley Devoto Shannon Stonemetz Filiz Genca Jeffery Kohlhoff Jason Newquist

Contact Meeting Met with project sponsor in Huntsville Learned more about the goals and expectations Discussed need for preliminary review prior to hardware implementation in spring Need to research processor options, FPGA software / hardware, possible launching motors, etc.

Wall-In-Space Requirement

Design Parameters General  Compatible with M261 launcher  Capable of being handled with arctic clothing and mittens  System Life: 10 yrs Min., 25 yrs Objective  All components unclassified  All units in Metric with English units in parenthesis

Design Parameters (cont.) Firing Envelope Altitude: -200ft MSL to 20,000ft MSL Platform Error: 19 milliradians Crosswind: 15 knots Velocity (Exit): 141 fps Max. Velocity (Wall in Space): 1978 fps Max. Detent Release Force: Minimum 13.5x missile weight Acceleration: 79g Max. Wall In Space

Design Parameters (cont.) Dimensions Weight: 34.4 lbs Max. Length: 79.7 inches Max., 71.7 inches Objective Outer Diameter: inches Max. Environmental Temperature (Storage): -65F to165F Temperature (Operating): -50F to 150F Humidity: constant 100% relative 75F

Weight Spec Sheet

M261 Characteristics Plastic nose cone, aluminum casing, integral fuze, explosion charge, 9 M73 submunitions Warhead fuze range settings of 500 – 7000 m Fuzed weight of M261 is 13.6 lbs Submunitions landing 5 degrees off-center have a 90% probability of casualties w/in 20 m radius (occurs 66% of the time)

14 April – Final Progress Rept. Previous project final status Simulation Implementation of ballistic algorithm Rebuilt for 6 degrees of freedom Prototype Shell program and interrupt service routine (ISR) for pulse-wave modulation Determination of I/O Algorithmic state charts Design review Supply procurement, assembly, demonstration

Previous Design Implementations Current Hydra-70 missile uses a screw- mount warhead design Suggested solution as per previous AMCOM team below: Avionics Module Side, Female Spline Warhead Side, Male Spline

Altera Cyclone FPGA Chipset The Cyclone device family offers the following features: ■ 2,910 to 20,060 LEs, see Table 1– 1 ■ Up to 294,912 RAM bits (36,864 bytes) ■ Supports configuration through low-cost serial configuration device ■ Support for LVTTL, LVCMOS, SSTL-2, and SSTL-3 I/O standards ■ Support for 66- and 33-MHz, 64- and 32-bit PCI standard ■ High-speed (640 Mbps) LVDS I/O support ■ Low-speed (311 Mbps) LVDS I/O support ■ 311-Mbps RSDS I/O support

Altera Cyclone FPGA Chipset (cont’d) ■ Up to two PLLs per device provide clock multiplication and phase shifting ■ Up to eight global clock lines with six clock resources available per logic array block (LAB) row ■ Support for external memory, including DDR SDRAM (133 MHz), FCRAM, and single data rate (SDR) SDRAM ■ Support for multiple intellectual property (IP) cores, including Altera® MegaCore® functions and Altera Megafunctions Partners Program (AMPPSM) megafunctions.