IT253: Computer Organization Lecture 9: Making a Processor: Single-Cycle Processor Design Tonga Institute of Higher Education.

Slides:



Advertisements
Similar presentations
361 datapath Computer Architecture Lecture 8: Designing a Single Cycle Datapath.
Advertisements

CS61C L26 Single Cycle CPU Datapath II (1) Garcia © UCB Lecturer PSOE Dan Garcia inst.eecs.berkeley.edu/~cs61c CS61C : Machine.
Savio Chau Single Cycle Controller Design Last Time: Discussed the Designing of a Single Cycle Datapath Control Datapath Memory Processor (CPU) Input Output.
Processor II CPSC 321 Andreas Klappenecker. Midterm 1 Tuesday, October 5 Thursday, October 7 Advantage: less material Disadvantage: less preparation time.
Inst.eecs.berkeley.edu/~cs61c UCB CS61C : Machine Structures Lecture 25 CPU design (of a single-cycle CPU) Sat Google in Mountain.
Microprocessor Design
Lec 17 Nov 2 Chapter 4 – CPU design data path design control logic design single-cycle CPU performance limitations of single cycle CPU multi-cycle CPU.
CS61C L25 Single Cycle CPU Datapath (1) Garcia © UCB Lecturer PSOE Dan Garcia inst.eecs.berkeley.edu/~cs61c CS61C : Machine.
ECE 232 L13. Control.1 ©UCB, DAP’ 97 ECE 232 Hardware Organization and Design Lecture 13 Control Design
CS61C L25 CPU Design : Designing a Single-Cycle CPU (1) Garcia, Fall 2006 © UCB T-Mobile’s Wi-Fi / Cell phone  T-mobile just announced a new phone that.
The Processor 2 Andreas Klappenecker CPSC321 Computer Architecture.
CS 61C L17 Control (1) A Carle, Summer 2006 © UCB inst.eecs.berkeley.edu/~cs61c/su06 CS61C : Machine Structures Lecture #17: CPU Design II – Control
CS61C L26 CPU Design : Designing a Single-Cycle CPU II (1) Garcia, Fall 2006 © UCB Lecturer SOE Dan Garcia inst.eecs.berkeley.edu/~cs61c.
Inst.eecs.berkeley.edu/~cs61c UCB CS61C : Machine Structures Lecture 25 CPU design (of a single-cycle CPU) Intel is prototyping circuits that.
CS61C L25 CPU Design : Designing a Single-Cycle CPU (1) Garcia, Spring 2007 © UCB Google Summer of Code  Student applications are now open (through );
EEM 486: Computer Architecture Lecture 3 Designing a Single Cycle Datapath.
CS61C L27 Single-Cycle CPU Control (1) Garcia, Spring 2010 © UCB inst.eecs.berkeley.edu/~cs61c UC Berkeley CS61C : Machine Structures Lecture 27 Single-cycle.
CS 61C L16 Datapath (1) A Carle, Summer 2004 © UCB inst.eecs.berkeley.edu/~cs61c/su05 CS61C : Machine Structures Lecture #16 – Datapath Andy.
CS 61C: Great Ideas in Computer Architecture (Machine Structures) Lecture 28: Single-Cycle CPU Datapath Control Part 1 Guest Lecturer: Sagar Karandikar.
361 control Computer Architecture Lecture 9: Designing Single Cycle Control.
ECE 232 L12.Datapath.1 Adapted from Patterson 97 ©UCBCopyright 1998 Morgan Kaufmann Publishers ECE 232 Hardware Organization and Design Lecture 12 Datapath.
CS61C L27 Single Cycle CPU Control (1) Garcia, Fall 2006 © UCB Wireless High Definition?  Several companies will be working on a “WirelessHD” standard,
The Processor Data Path & Control Chapter 5 Part 1 - Introduction and Single Clock Cycle Design N. Guydosh 2/29/04.
CS3350B Computer Architecture Winter 2015 Lecture 5.6: Single-Cycle CPU: Datapath Control (Part 1) Marc Moreno Maza [Adapted.
IT253: Computer Organization Lecture 10: Making a Processor: Control Signals Tonga Institute of Higher Education.
EEM 486: Computer Architecture Designing Single Cycle Control.
Lec 15Systems Architecture1 Systems Architecture Lecture 15: A Simple Implementation of MIPS Jeremy R. Johnson Anatole D. Ruslanov William M. Mongan Some.
Computer Organization CS224 Fall 2012 Lesson 22. The Big Picture  The Five Classic Components of a Computer  Chapter 4 Topic: Processor Design Control.
ECE 445 – Computer Organization
EEM 486: Computer Architecture Designing a Single Cycle Datapath.
CDA 3101 Fall 2013 Introduction to Computer Organization
CPE 442 single-cycle datapath.1 Intro. To Computer Architecture CpE242 Computer Architecture and Engineering Designing a Single Cycle Datapath.
W.S Computer System Design Lecture 4 Wannarat Suntiamorntut.
Datapath and Control Unit Design
CS3350B Computer Architecture Winter 2015 Lecture 5.7: Single-Cycle CPU: Datapath Control (Part 2) Marc Moreno Maza [Adapted.
EE 3755 Datapath Presented by Dr. Alexander Skavantzos.
By Wannarat Computer System Design Lecture 4 Wannarat Suntiamorntut.
COM181 Computer Hardware Lecture 6: The MIPs CPU.
Csci 136 Computer Architecture II –Single-Cycle Datapath Xiuzhen Cheng
EEM 486: Computer Architecture Lecture 3 Designing Single Cycle Control.
CS 61C: Great Ideas in Computer Architecture (Machine Structures) Single-Cycle CPU Datapath & Control Part 2 Instructors: Krste Asanovic & Vladimir Stojanovic.
Single Cycle Controller Design
CS161 – Design and Architecture of Computer Systems
Designing a Single-Cycle Processor
IT 251 Computer Organization and Architecture
Introduction CPU performance factors
(Chapter 5: Hennessy and Patterson) Winter Quarter 1998 Chris Myers
Morgan Kaufmann Publishers The Processor
Morgan Kaufmann Publishers
Processor (I).
CS/COE0447 Computer Organization & Assembly Language
CpE242 Computer Architecture and Engineering Designing a Single Cycle Datapath Start: X:40.
Single Cycle CPU Design
CSCI206 - Computer Organization & Programming
Lecturer PSOE Dan Garcia
Instructors: Randy H. Katz David A. Patterson
Morgan Kaufmann Publishers The Processor
The Single Cycle Datapath
Rocky K. C. Chang 6 November 2017
CS152 Computer Architecture and Engineering Lecture 8 Designing a Single Cycle Datapath Start: X:40.
COMS 361 Computer Organization
inst.eecs.berkeley.edu/~cs61c-to
CSC3050 – Computer Architecture
Computer Architecture Processor: Datapath
Prof. Giancarlo Succi, Ph.D., P.Eng.
Instructors: Randy H. Katz David A. Patterson
COMS 361 Computer Organization
What You Will Learn In Next Few Sets of Lectures
Designing a Single-Cycle Processor
Presentation transcript:

IT253: Computer Organization Lecture 9: Making a Processor: Single-Cycle Processor Design Tonga Institute of Higher Education

The big picture Where are we now in the computer picture? The datapath is the way the computer implements the instruction set (like MIPS) It is obviously an important part of the processor. When we understand the datapath, we will understand most of the processor

MIPS and the datapath Remember MIPS uses instruction formatting to convert text into binary numbers. These numbers will be what the datapath reads in and executes. In MIPS they are 32 bits long and have different fields. This is how we will build our processor

Building a Datapath So what hardware pieces (gates and circuits) do we need to implement the MIPS instructions? We will need an Adder, a MUX, and an ALU

Memory Circuits So far all the circuits we have made will give us an output, which we can use to perform operations We also need a way to save memory (like a register). There are a few ways that we can save a value in a circuit. The output of these circuits that remember values is the result of the value inside. These are called “sequential” circuits

Building a Datapath: The Clock We will be talking about devices called clocks in this chapter. Because computers need things to happen in a certain order, they need to be synchronized To be synchronized, computers will use clocks which are a series of pulses that has a very accurate width and interval between pulses The time interval between pulses is called the clock cycle time. A 500 MHz processor has a clock cycle of 2 nanoseconds. This means every 2 nano-seconds (2 billionths of a second) the processor can execute another operation

Set-Reset Latch One simple memory element is called the Set- Reset Latch

Tri-State Driver A tri-state driver is a one-directional switch. When it is enabled (E=1), output = input When it is not enabled (E=0), the output is physically disconnected from the gate's internal circuitry. This state is normally called "floating" The output is neither logic high or low, instead it floats and appears as a very high resistance on the circuit, in effect the Tri-state device is disconnected from the circuit. This will allow whatever value was Q before to remain

What can we do with those? With memory elements and the tri-state driver we can make circuits that save memory addresses and decode them. We can also save values in registers We can also use a tri-state driver to choose one thing from among many, like on a data bus ( a wire that connects many devices).

Building a Datapath: Memory We need a way to store things The storage element we will use is called a “register” This is like the memory element we talked about in MIPS The Set-Reset Latch. “Register” memory uses N bits for input and output. There must be a "Write Enable" option. If the input to "Write enable" is: 1 - then the register will output the numbers from Data In 0 – then the output will not change from what it was before

Building a Datapath: Lots of Memory We need to store 32 registers, so we create what is called a “register file” A register file is 32 registers put together into one little box It also has two 32 bit outputs (busA and busB) and one 32 bit input (busW) RA selects the register that will go onto bus A RB selects the register that will go onto bus B RW selects the register that will be changed by the input (busW) if Write Enable = 1 Clk = Clock – the input that will run the cycle of the register file. After a clock cycle, something will have happened (either output or a write)

Datapath: Putting pieces together With these pieces we can start to get a feel for what the datapath of the processor will look like. The Clock will determine the access and run times of every pieces. They all run on the same clock

Datapath: Getting Instructions The CPU needs a way to fetch instructions from memory. The steps to get instructions are: –Fetch instruction from memory –Update program counter (+4 if sequential. –If there is a branch, jump somewhere else)

What’s happening behind instructions Example: Register-Register function: add 1.Get the instruction from memory -mem[PC] 2.Perform the operation -R[rd] = R[rs] + R[rt] 3.Go to next instruction -PC = PC + 4

Datapath for Register-Register So how do we make the hardware to do register- register… -Ra, Rb and Rw come from the rs, rt and rd fields in the instruction format. -RegWr and ALUctr come from decoding the op and funct parts of the code

Register-Register Timing

Register-Immediate Instructions Example: –OR Immediate – "ori $a0,$s1,256" –Fetch instruction from memory –R[rt] = R[rs] | (extend zero fill for first 16 bits and immediate) –PC = PC + 4 The difference from the register-register instruction is that we must add two MUXs in order to choose the correct registers

Register-Immediate Instruction

Load Instructions How does the datapath need to change for load instructions? We need to add a MUX to choose an address from memory instead of a register

Store Instructions For store instructions we just need to connect a line to the input for memory

Branch Instructions Branch instructions have different steps and a more complicated datapath to follow Example: beq rs,rt,immediate 1.Fetch instruction from memory 2.Calculate branch condition 3.If condition is true than go to the new address 1.PC = PC+4+Immediate 4.If condition is not true, then just PC+4

Branch Datapath To use branch instruction in the datapath we need to connect to the PC Then do a compare of Rs and Rt (by subtracting) and check if the subtract = 0 (using the ALU zero operation). Why do we use this?

The PC and addresses Hopefully you have noticed by now that all our addresses with the PC are multiples of 4. That is because each instruction is 32 bits and the PC does byte addressing (1 byte= 8 bit * 4 = 32) That also means that the last two bits of any address are always zero. 4 in binary = 100, 8 in binary = 1000, 12 in binary = 1100 So we actually don’t need to save those last two bits if they are always zero! We use the following notation to show this: –PC - This means use bits 0-31, but ignore the first 2 –When we do PC increment, we can just add 1, instead of 4, because we have thrown away the first 2 bits. –The computer only needs a 30 bit PC, instead of 32 (cheaper and faster now) and we will just add “00” to the end when the time comes

Jump Instruction with 30 bits Example: j target 1.Load instruction from memory 2.Change the PC = PC = NewAddress NewAddress = “0000” + 26 bits from the target + “00”

Jump Datapath in the Instruction Fetch Unit 0 0

Putting it all together – Our full datapath We still need to add control signals for the processor to be complete

Summary This chapter was about the datapath of the processor. It showed how to put gates and circuits together in order to build a way for instructions to be executed in a computer We still need to look at the other part of the processor: control The control will let us know how the processor chooses different ways to control operations