Non-stitch Triple Patterning- Aware Routing Based on Conflict Graph Pre-coloring Po-Ya Hsu Yao-Wen Chang.

Slides:



Advertisements
Similar presentations
Linear Time Algorithm to Find All Relocation Positions for EUV Defect Mitigation Yuelin Du, Hongbo Zhang, Qiang Ma and Martin D. F. Wong ASPDAC13.
Advertisements

Gate Sizing for Cell Library Based Designs Shiyan Hu*, Mahesh Ketkar**, Jiang Hu* *Dept of ECE, Texas A&M University **Intel Corporation.
Optimization of Placement Solutions for Routability Wen-Hao Liu, Cheng-Kok Koh, and Yih-Lang Li DAC’13.
Native-Conflict-Aware Wire Perturbation for Double Patterning Technology Szu-Yu Chen, Yao-Wen Chang ICCAD 2010.
Topology-Aware Buffer Insertion and GPU-Based Massively Parallel Rerouting for ECO Timing Optimization Yen-Hung Lin, Yun-Jian Lo, Hian-Syun Tong, Wen-Hao.
Hsi-An Chien Ting-Chi Wang Redundant-Via-Aware ECO Routing ASPDAC2014.
Meng-Kai Hsu, Sheng Chou, Tzu-Hen Lin, and Yao-Wen Chang Electronics Engineering, National Taiwan University Routability Driven Analytical Placement for.
Methodology for Standard Cell Compliance and Detailed Placement for Triple Patterning Lithography Bei Yu, Xiaoqing Xu, JhihRong Gao, David Z. Pan.
National Tsing Hua University Po-Yang Hsu,Hsien-Te Chen,
Coupling-Aware Length-Ratio- Matching Routing for Capacitor Arrays in Analog Integrated Circuits Kuan-Hsien Ho, Hung-Chih Ou, Yao-Wen Chang and Hui-Fang.
Multi-Project Reticle Floorplanning and Wafer Dicing Andrew B. Kahng 1 Ion I. Mandoiu 2 Qinke Wang 1 Xu Xu 1 Alex Zelikovsky 3 (1) CSE Department, University.
GREMA: Graph Reduction Based Efficient Mask Assignment for Double Patterning Technology Yue Xu, Chris Chu Iowa State University Form ICCAD2009.
An Optimal Algorithm of Adjustable Delay Buffer Insertion for Solving Clock Skew Variation Problem Juyeon Kim, Deokjin Joo, Taehan Kim DAC’13.
Ahmed Awad Atsushi Takahash Satoshi Tanakay Chikaaki Kodamay ICCAD’14
An ILP-based Automatic Bus Planner for Dense PCBs P. C. Wu, Q. Ma and M. D. F. Wong Department of Electrical and Computer Engineering, University of Illinois.
Author: David He, Astghik Babayan, Andrew Kusiak By: Carl Haehl Date: 11/18/09.
TPL-aware displacement-driven detailed placement refinement with coloring constraints Tao Lin and Chris Chu Iowa State University 1.
MCFRoute: A Detailed Router Based on Multi- Commodity Flow Method Xiaotao Jia, Yici Cai, Qiang Zhou, Gang Chen, Zhuoyuan Li, Zuowei Li.
Dual Graph-Based Hot Spot Detection Andrew B. Kahng 1 Chul-Hong Park 2 Xu Xu 1 (1) Blaze DFM, Inc. (2) ECE, University of California at San Diego.
Routability-Driven Blockage-Aware Macro Placement Yi-Fang Chen, Chau-Chin Huang, Chien-Hsiung Chiou, Yao-Wen Chang, Chang-Jen Wang.
: Grid graph :Draw two rays from each concave point Rays are divided into non-intersected ray-segments Conflict pair: two ray segments from the same point.
Yield- and Cost-Driven Fracturing for Variable Shaped-Beam Mask Writing Andrew B. Kahng CSE and ECE Departments, UCSD Xu Xu CSE Department, UCSD Alex Zelikovsky.
Design Bright-Field AAPSM Conflict Detection and Correction C. Chiang, Synopsys A. Kahng, UC San Diego S. Sinha, Synopsys X. Xu, UC San Diego A. Zelikovsky,
1 An Empirical Study on Large-Scale Content-Based Image Retrieval Group Meeting Presented by Wyman
A Cell-Based Row-Structure Layout Decomposer for Triple Patterning Lithography Hsi-An Chien, Szu-Yuan Han, Ye-Hong Chen, and Ting-Chi Wang Department of.
Sambuddha Bhattacharya Subramanian Rajagopalan Shabbir H. Batterywala Fixing Double Patterning Violations With Look-Ahead ASD-DAC’14.
Triple Patterning Aware Detailed Placement With Constrained Pattern Assignment Haitong Tian, Yuelin Du, Hongbo Zhang, Zigang Xiao, Martin D.F. Wong.
A Resource-level Parallel Approach for Global-routing-based Routing Congestion Estimation and a Method to Quantify Estimation Accuracy Wen-Hao Liu, Zhen-Yu.
Constrained Pattern Assignment for Standard Cell Based Triple Patterning Lithography H. Tian, Y. Du, H. Zhang, Z. Xiao, M. D.F. Wong Department of ECE,
Optimally Minimizing Overlay Violation in Self-aligned Double Patterning Decomposition for Row-based Standard Cell Layout in Polynomial Time Z. Xiao, Y.
Hsiu-Yu Lai Ting-Chi Wang A TPL-Friendly Legalizer for Standard Cell Based Design SASIMI ‘15.
MGR: Multi-Level Global Router Yue Xu and Chris Chu Department of Electrical and Computer Engineering Iowa State University ICCAD
A Topology-based ECO Routing Methodology for Mask Cost Minimization Po-Hsun Wu, Shang-Ya Bai, and Tsung-Yi Ho Department of Computer Science and Information.
Graph Indexing: A Frequent Structure­ based Approach Authors:Xifeng Yan†, Philip S‡. Yu, Jiawei Han†
Xin-Wei Shih and Yao-Wen Chang.  Introduction  Problem formulation  Algorithms  Experimental results  Conclusions.
CAFE router: A Fast Connectivity Aware Multiple Nets Routing Algorithm for Routing Grid with Obstacles Y. Kohira and A. Takahashi School of Computer Science.
TSV-Aware Analytical Placement for 3D IC Designs Meng-Kai Hsu, Yao-Wen Chang, and Valerity Balabanov GIEE and EE department of NTU DAC 2011.
1 Global Routing Method for 2-Layer Ball Grid Array Packages Yukiko Kubo*, Atsushi Takahashi** * The University of Kitakyushu ** Tokyo Institute of Technology.
A* Lasso for Learning a Sparse Bayesian Network Structure for Continuous Variances Jing Xiang & Seyoung Kim Bayesian Network Structure Learning X 1...
K.Yuan, J.Yang and D.Pan ECE Dept. Univ. of Texas at Austin
2004, 9/1 1 Optimal Content-Based Video Decomposition for Interactive Video Navigation Anastasios D. Doulamis, Member, IEEE and Nikolaos D. Doulamis, Member,
VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 5: Global Routing © KLMH Lienig 1 EECS 527 Paper Presentation High-Performance.
New Modeling Techniques for the Global Routing Problem Anthony Vannelli Department of Electrical and Computer Engineering University of Waterloo Waterloo,
Efficient Multi-Layer Obstacle- Avoiding Rectilinear Steiner Tree Construction Chung-Wei Lin, Shih-Lun Huang, Kai-Chi Hsu,Meng-Xiang Li, Yao-Wen Chang.
Thermal-aware Steiner Routing for 3D Stacked ICs M. Pathak and S.K. Lim Georgia Institute of Technology ICCAD 07.
Bus-Pin-Aware Bus-Driven Floorplanning B. Wu and T. Ho Department of Computer Science and Information Engineering NCKU GLSVLSI 2010.
ECO Timing Optimization Using Spare Cells Yen-Pin Chen, Jia-Wei Fang, and Yao-Wen Chang ICCAD2007, Pages ICCAD2007, Pages
Tao Lin Chris Chu TPL-Aware Displacement- driven Detailed Placement Refinement with Coloring Constraints ISPD ‘15.
Huang-Yu Chen †, Mei-Fang Chiang †, Yao-Wen Chang † Lumdo Chen ‡, and Brian Han ‡ Novel Full-Chip Gridless Routing Considering Double-Via Insertion † The.
Exact routing for digital microfluidic biochips with temporary blockages OLIVER KESZOCZE ROBERT WILLE ROLF DRECHSLER ICCAD’14.
Dept. of Electrical and Computer Engineering The University of Texas at Austin E-Beam Lothography Stencil Planning and Optimization wit Overlapped Characters.
1 Efficient Obstacle-Avoiding Rectilinear Steiner Tree Construction Chung-Wei Lin, Szu-Yu Chen, Chi-Feng Li, Yao-Wen Chang, Chia-Lin Yang National Taiwan.
A SAT-Based Routing Algorithm for Cross-Referencing Biochips Ping-Hung Yuh 1, Cliff Chiung-Yu Lin 2, Tsung- Wei Huang 3, Tsung-Yi Ho 3, Chia-Lin Yang 4,
Self-Aligned Double Patterning Decomposition for Overlay Minimization and Hot Spot Detection H. Zhang, Y. Du, M. D.F. Wong, R. Topaloglu Dept. of ECE,
The Colorful Traveling Salesman Problem Yupei Xiong, Goldman, Sachs & Co. Bruce Golden, University of Maryland Edward Wasil, American University Presented.
1 ε -Optimal Minimum-Delay/Area Zero-Skew Clock Tree Wire-Sizing in Pseudo-Polynomial Time Jeng-Liang Tsai Tsung-Hao Chen Charlie Chung-Ping Chen (National.
Hsing-Chih Chang Chien Hung-Chih Ou Tung-Chieh Chen Ta-Yu Kuan Yao-Wen Chang Double Patterning Lithography-Aware Analog Placement.
An Efficient Linear Time Triple Patterning Solver Haitong Tian Hongbo Zhang Zigang Xiao Martin D.F. Wong ASP-DAC’15.
PARR:Pin Access Planning and Regular Routing for Self-Aligned Double Patterning XIAOQING XU BEI YU JHIH-RONG GAO CHE-LUN HSU DAVID Z. PAN DAC’15.
Simultaneous Analog Placement and Routing with Current Flow and Current Density Considerations H.C. Ou, H.C.C. Chien and Y.W. Chang Electronics Engineering,
SocialVoD: a Social Feature-based P2P System Wei Chang, and Jie Wu Presenter: En Wang Temple University, PA, USA IEEE ICPP, September, Beijing, China1.
Yen-Ting Yu Iris Hui-Ru Jiang Yumin Zhang Charles Chiang DRC-Based Hotspot Detection Considering Edge Tolerance and Incomplete Specification ICCAD’14.
Chin-Hsiung Hsu, Yao-Wen Chang, and Sani Rechard Nassif From ICCAD09.
Maze Routing Algorithms with Exact Matching Constraints for Analog and Mixed Signal Designs M. M. Ozdal and R. F. Hentschke Intel Corporation ICCAD 2012.
BOB-Router: A New Buffering-Aware Global Router with Over-the-Block Routing Resources Yilin Zhang1, Salim Chowdhury2 and David Z. Pan1 1 Department of.
System in Package and Chip-Package-Board Co-Design
Constraint Programming for the Diameter Constrained Minimum Spanning Tree Problem Thiago F. Noronha Celso C. Ribeiro Andréa C. Santos.
1 Double-Patterning Aware DSA Template Guided Cut Redistribution for Advanced 1-D Gridded Designs Zhi-Wen Lin and Yao-Wen Chang National Taiwan University.
11 Yibo Lin 1, Xiaoqing Xu 1, Bei Yu 2, Ross Baldick 1, David Z. Pan 1 1 ECE Department, University of Texas at Austin 2 CSE Department, Chinese University.
Double Patterning Samuel Johnson 11/6/18.
Presentation transcript:

Non-stitch Triple Patterning- Aware Routing Based on Conflict Graph Pre-coloring Po-Ya Hsu Yao-Wen Chang

Outline INTRODUCTION THE NON-STITCH TRIPLE PATTERNING-AWARE ROUTING ALGORITHM EXPERIMENTAL RESULTS CONCLUSIONS

INTRODUCTION Before the next-generation lithography technologies are mature for production, multiple patterning lithography is a dominating solution for nanometer circuit designs [9].

INTRODUCTION Double patterning lithography is the simplest case of multiple patterning lithography and can reduce the feature size down below 32nm [4] by using two photo masks. Triple patterning lithography uses one more mask to manufacture a layout and becomes a feasible method to improve the feature size down below 14nm [15], even below 10nm [14].

INTRODUCTION An earlier work shows that most of the hard-to-decompose patterns are generated from the detailed routing stage. Thus it is desirable to address the multiple patterning-aware routing problem that considers the multiple patterning decomposability during routing.

INTRODUCTION Coloring (mask) conflicts are resolved by stitch insertion which is a layout decomposition solution partitioning a single pattern into multiple photo masks. Stitch insertion may incur stitch overlay errors, which would significantly reduce yield and increase cost.

INTRODUCTION Leading foundries such as TSMC directly prohibit stitch insertion in their design methodologies. How to minimize color conflict counts without any stitch insertion during routing becomes a timely issue for industry production.

THE NON-STITCH TRIPLE PATTERNING-AWARE ROUTING ALGORITHM Our non-stitch triple patterning-aware routing algorithm has to solve the two main problems: (1) conflict graph pre-coloring and (2)pre-coloring-based non-stitch routing

Potential Color Difference Estimation We use a global-routing-based estimator with A*-search routing to find possible routing paths.

Potential Color Difference Estimation

Conflict Graph Construction

Conflict Graph Pre-coloring Algorithm We formulate the pre-coloring problem into the maximum 3-cut problem. Recently, Ling et al. [13] proposed a variable neighborhood stochastic (VNS)meta-heuristic which can obtain high-quality solutions efficiently. In our conflict graph pre-coloring algorithm, we use the VNS meta- heruistic for its efficiency.

Conflict Graph Pre-coloring Algorithm

Pre-coloring-based Non-stitch Routing Algorithm To eliminate the self-crossing net problem, our graph model has the property that a net will not change its color during routing and will not generate any self-crossing path. In our graph model, each grid node at the coordinate (x, y, z) contains three graph vertices.

Pre-coloring-based Non-stitch Routing Algorithm

Feedback Pre-coloring-based Non-stitch Routing Scheme

EXPERIMENTAL RESULTS We implemented our triple patterning-aware non-stitch routing algorithm in the C++ programming language and conducted our experiments on a Linux machine with 24 Intel 2.00 GHz CPUs and 72 GB memory.

EXPERIMENTAL RESULTS

CONCLUSIONS This paper has presented the first non-stitch triple patterning-aware routing algorithm. Compared with the extension of the state-of-the-art work [16], the experimental results have shown that our algorithm can obtain non- stitch routing results with no color conflicts effectively and efficiently.