1 IMEC / KHBO June 2004 IMEC / KHBO. 2 Becoming an associated laboratory of IMEC was possible due to the expertise built up in the Microelectronics group.

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Presentation transcript:

1 IMEC / KHBO June 2004 IMEC / KHBO

2 Becoming an associated laboratory of IMEC was possible due to the expertise built up in the Microelectronics group in the following fields:  analogue and digital IC-design  System integration (System-on-board, SoC)  Higher level system integration methodologies

3 Design methodologies “nature of systems” change Past - nowFuture Small block reuseIntelligent test benches Large block reuseEmbedded system-level IC implementation toolstechnology PLD System-on-Chip

4 Design history : evolution in the past

5 From idea to a specification Hierarchical design flow

6 Small block IP : basic building blocks SCHEMATICLAYOUT

7 Large block IP : 12-bit ADC 12-bit ADC current mode folding and interpolation 50 MHz 0.35 µm CMOS AME 34,5 mm 2 for telecom applications

8 System-on-Board

9 Example system-on-board (Coware) Demonstrator for Coware development tools

10 ESA project for PCDF-equipment in ISS International Space Station (ISS) Example of complete system development

11 Integration in the space-module

12 System-on-chip

13 Example System-on-chip (FPLSIC) FPLSIC = Field Programmable Level System Integration Circuit 3 basic components integrated in 1 integrated circuit : SRAM PFGA Processor Co-verification Build in power management

14 FPSLIC embedded blocks Configurable SRAM SRAM interface AVR/AT40K interface Software configurable interface between blocks already implemented Pre-implemented Interface blocks save FPGA gates AT40K FPGA 8 Bit RISC MCU

15 User-Defined Logic Spectrum ATF22V10 ATF16V8 ATF20V8 ATV2500B ATF1500 Fam ATV750B AT6000 AT40K ATL25 Series ATL35 Series ATL50 Series ATL60 Series Decoders, Glue Logic State machines, Timing, Control RAM/Logic, Computing, Co-processing System Level Integration Density Macrocells 0.25, 0.35, 0.5, 0.6  Analog / Digital Analog / Digital/ NV Memory, RF PAL- Type CPLD FPGA Gate Array Custom ASIC FPSLIC AT94K Cell based ASIC High Volume/Low Cost

16 FPLSIC design flow from Atmel

17 Co-verification, why ? Iteration Loop 1 to 3 Months Hardware Development Software Development System Integration Physical Implementation

18 Co-verification Physical Implementation Hardware Development Software Development Release to Manufacturing System Integration System Designer Iteration Loop 1 to 3 Hours Co-Verification

19 Student diploma work with FPLSIC Low current contact sensing for reliability test of bonding wires

20 Research Project : Test set-up for the study of mechanical stress in chips Test Equipment Oven + Wafer/Chip under test

21 Contact If you want to be informed about possible SOCRATES assignments PLEASE CONTACT: Ing.D.Gevaert, MPhil Zeedijk 101, B-8400 Oostende Tel 059/