Introduction to FPGA Tools ECE 645 – Computer Arithmetic

Design process (1) Specification (Lab Experiments) Design and implement a simple unit permitting to speed up encryption with RC5-similar cipher with fixed key set on 8031 microcontroller. Unlike in the experiment 5, this time your unit has to be able to perform an encryption algorithm by itself, executing 32 rounds….. Specification (Lab Experiments) VHDL description (Your Source Files) Library IEEE; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity RC5_core is port( clock, reset, encr_decr: in std_logic; data_input: in std_logic_vector(31 downto 0); data_output: out std_logic_vector(31 downto 0); out_full: in std_logic; key_input: in std_logic_vector(31 downto 0); key_read: out std_logic; ); end AES_core; Functional simulation Synthesis Post-synthesis simulation ECE 645 – Computer Arithmetic

Design process (2) Implementation Timing simulation Configuration On chip testing ECE 645 – Computer Arithmetic

Design Process control from Active-HDL ECE 645 – Computer Arithmetic

Simulation Tools Many others… ECE 645 – Computer Arithmetic

ECE 645 – Computer Arithmetic

ECE 645 – Computer Arithmetic

Synthesis Tools … and others ECE 645 – Computer Arithmetic

Logic Synthesis VHDL description Circuit netlist architecture MLU_DATAFLOW of MLU is signal A1:STD_LOGIC; signal B1:STD_LOGIC; signal Y1:STD_LOGIC; signal MUX_0, MUX_1, MUX_2, MUX_3: STD_LOGIC; begin A1<=A when (NEG_A='0') else not A; B1<=B when (NEG_B='0') else not B; Y<=Y1 when (NEG_Y='0') else not Y1; MUX_0<=A1 and B1; MUX_1<=A1 or B1; MUX_2<=A1 xor B1; MUX_3<=A1 xnor B1; with (L1 & L0) select Y1<=MUX_0 when "00", MUX_1 when "01", MUX_2 when "10", MUX_3 when others; end MLU_DATAFLOW; ECE 645 – Computer Arithmetic

Features of synthesis tools Interpret RTL code Produce synthesized circuit netlist in a standard EDIF format Give preliminary performance estimates Some can display circuit schematics corresponding to EDIF netlist ECE 645 – Computer Arithmetic

Implementation After synthesis the entire implementation process is performed by FPGA vendor tools ECE 645 – Computer Arithmetic

ECE 645 – Computer Arithmetic

Translation Circuit netlist Timing Constraints Native Constraint File Synthesis Circuit netlist Timing Constraints Constraint Editor Native Constraint File Electronic Design Interchange Format EDIF NCF UCF User Constraint File Translation NGD Native Generic Database file ECE 645 – Computer Arithmetic

Sample UCF File # # Constraints generated by Synplify Pro 7.3.3, Build 039R # Period Constraints #Begin clock constraints #End clock constraints # Output Constraints # Input Constraints # Location Constraints # End of generated constraints NET "clock" LOC = "P88"; NET "control(0)" LOC = "P50"; NET "control(1)" LOC = "P48"; NET "control(2)" LOC = "P42"; NET "reset" LOC = "P93"; NET "segments(0)" LOC = "P67"; NET "segments(1)" LOC = "P39"; NET "segments(2)" LOC = "P62"; NET "segments(3)" LOC = "P60"; NET "segments(4)" LOC = "P46"; NET "segments(5)" LOC = "P57"; NET "segments(6)" LOC = "P49"; ECE 645 – Computer Arithmetic

Pin Assignment FPGA LAB2 CLOCK CONTROL(0) CONTROL(2) CONTROL(1) RESET SEGMENTS(0) SEGMENTS(1) SEGMENTS(2) SEGMENTS(3) SEGMENTS(4) SEGMENTS(5) SEGMENTS(6) P39 P42 P46 P48 P49 P50 P57 P60 P62 P67 P88 P93 FPGA ECE 645 – Computer Arithmetic

XSA Board Connectivity ECE 645 – Computer Arithmetic

Constraints Editor ECE 645 – Computer Arithmetic

Circuit netlist ECE 645 – Computer Arithmetic

Mapping LUT0 LUT4 LUT1 FF1 LUT5 LUT2 FF2 LUT3 ECE 645 – Computer Arithmetic

Placing FPGA CLB SLICES ECE 645 – Computer Arithmetic

Routing FPGA Programmable Connections ECE 645 – Computer Arithmetic

Static Timing Analyzer Performs static analysis of the circuit performance Reports critical paths with all sources of delays Determines maximum clock frequency ECE 645 – Computer Arithmetic

Static Timing Analysis Critical Path – The Longest Path From Outputs of Registers to Inputs of Registers D Q in clk out tP logic tCritical = tP FF + tP logic + tS FF ECE 645 – Computer Arithmetic

Static Timing Analysis Min. Clock Period = Length of The Critical Path Max. Clock Frequency = 1 / Min. Clock Period ECE 645 – Computer Arithmetic

Configuration Once a design is implemented, you must create a file that the FPGA can understand This file is called a bit stream: a BIT file (.bit extension) The BIT file can be downloaded directly to the FPGA, or can be converted into a PROM file which stores the programming information ECE 645 – Computer Arithmetic

Resources & Required Reading Spartan FPGA devices Xilinx Spartan-3 FPGA Family: Complete Data Sheets Module 1: Introduction & Ordering Information Module 2: Functional Description Xilinx Virtex-II 1.5V FPGA Family: ECE 645 – Computer Arithmetic

Resources & Required Reading FPGA Tools Integrated Interfaces: Active-HDL with Synplify® http://www.aldec.com/Previews/active_synplify.htm Integrated Synthesis and Implementation http://www.aldec.com/Previews/synthesis_implementation.htm ECE 645 – Computer Arithmetic

Enough Talking Let’s Get To It !!Brace Yourselves!! Hands-on Session Enough Talking Let’s Get To It !!Brace Yourselves!! ECE 645 – Computer Arithmetic

ALU Schematic arith [1:0] A[3:0] B[3:0] A + B A - B 1 A <<< 1 A - B 1 A <<< 1 2 A >>> 1 3 1 ar_log 1 Y [3:0] neg_Y logic [1:0] A and B A or B 1 A xor B 2 A xnor B 3 ECE 645 – Computer Arithmetic

Questions? ECE 645 – Computer Arithmetic