Northeastern U N I V E R S I T Y 1 Design and Test of Fault Tolerant Quantum Dot Cellular Automata Electrical and Computer Department

Northeastern U N I V E R S I T Y 2 Outline  Introduction: QCA Technology  Example QCA circuits  Testing Majority Voter, Networks of MV  DFT for QCA  Novel Complex Universal Gate: AOI (And-OR- Inverter) Gate  Synthesis with QCA technology  Future Research Directions

Northeastern U N I V E R S I T Y 3 QCA Introduction (I) Motivation » Approaching physical limits of CMOS sizing » Alternative technologies need to be investigated. » QCA as a nano scale solution New method of computation and information transformation. Current Manufacturing Status of QCA » Micro-sized QCA devices latch and 2-bit shift register have been manufactured » Research focused on molecular QCA devices for room temperature operation. Initial analysis of a simple molecular systems reported.

Northeastern U N I V E R S I T Y 4 QCA Introduction (II) Speed* nm spacing: 25GHz nm spacing: 2.5THz Clocking Zone Size* » assuming 5x20 cell zone size In 42 nm: 0.16sq  m In 4.2 nm: sq  m » In 0.05  m CMOS: Size of typical transistor = 0.56sq  m Top area of minimum wire contact =0.01sq  m * In “Architectural Issues and Possibilities in Quantum Cellular Automata (QCA)” by M.T.Niemier and P.M.Kogge in NSF

Northeastern U N I V E R S I T Y 5 QCA Cell QCA cell consisting of 4 “dots” and 2 extra electrons; Information stored not as voltage level » Positions of electrons Coulomb interaction between cells No current in information transformation Very low power dissipation. Binary ‘0’Binary ‘1’ Quantum dot electron Rotated cells QCA cell

Northeastern U N I V E R S I T Y 6 Cell Interaction Information is transferred by the Coulomb Interaction. Input Cell State Propagation Direction Binary Wire QCA cell

Northeastern U N I V E R S I T Y 7 Basic QCA Devices A B C Majority Voter: F=AB+AC+BC F Coplanar Wire Crossing Inverter QCA cell

Northeastern U N I V E R S I T Y 8 4-phase Clocking QCA cell Switch Hold ReleaseRelax Clock Field Strength Clock Zone Phase Timing in 4 time zones 4 phases in each clock zone State Propagation Direction Zone 1Zone 2Zone 3 Zone 4

Northeastern U N I V E R S I T Y 9 QCA Full Adder The full adder consists of » 3 MVs » 2 Inverter Different Shades of color represent clock zones

Northeastern U N I V E R S I T Y 10 QCA Memory Cell Memory stored in a loop. Different Shades of color represent clock zones

Northeastern U N I V E R S I T Y 11 Majority Voter (MV) Implement logic AND/OR functions, by setting an input to: » 0 for AND, » 1 for OR gate. A B C F MV Input A Input B Input C Device cell Output F Output F as the majority of inputs: F=MV(A,B,C)=AB+AC+BC

Northeastern U N I V E R S I T Y 12 Test Sets for MV No built-in VDD or ground lines in QCA designs. 2 extra inputs connected to logic “1” and logic “0” » Called control lines connected to one MV input » Implementing AND and OR logic functions. 0 A B A B A B MV U0 1 A B MV U1

Northeastern U N I V E R S I T Y 13 Testing MV 100% single stuck-at fault test set: » ABC= (010, 100, 101, 110) » Fault List: A/1 (A stuck-at 1), A/0, B/1, B/0, C/1, C/0, d/1, d/0, Z/1, and Z/0 100% single stuck-at fault test set: » ABCU 0 U 1 = (11100, 00011) » Fault List: A/0, B/0, C/0, d/0, and Z/0 Additionally, » ABCU 0 U 1 = (10011, 01100) detects all faults on U 0 U 1

Northeastern U N I V E R S I T Y 14 General Test Set for a Network of MVs A logic network composed only of AND and OR gates » AND/OR implemented using QCA MVs. 2 extra control inputs other than primary inputs: » U0,U1 A B C D E F g h i j Z MV1 MV2 MV3 MV4 MV5 U1 1 U0 0

Northeastern U N I V E R S I T Y 15 General Test Set for a Network of MVs Only 2 vectors needed to detect all SSFs » The 1st test vector sets all primary inputs to “0” sets 2 control inputs to “1” (all MVs  OR gates) detects all (multiple) stuck-at-1 faults » The 2nd test vector sets all primary inputs to “1” sets 2 control inputs to “0” (all MVs  AND gates) detects all (multiple) stuck-at-0 faults

Northeastern U N I V E R S I T Y 16 General Test Set for a Network of MVs Additional Vectors needed to detect faults in control lines (U 0 U 1 ) Conventional (combinational) ATPG tools used » MV replaced by a hierarchical cell implementing the majority function. » Network of MVs transformed into a hierarchical gate-level netlist. » Use ATPG for the pin faults on the control inputs

Northeastern U N I V E R S I T Y 17 Testing Networks AND, OR, INV Universal Logic: AND, OR & INV INVs prevent fault propagation by 2 test vectors A B C D E F g h i1i1 j Z i2i2 A B C D E F g h j Z MV1 MV 2 MV3 MV4 MV5 1 U0 0 i1i1 i2i2 U1 Without INV: ABCDEFU 0 U 1 = ( detects all stuck-at-1 faults With INV: ABCDEFU 0 U 1 = ( ) cannot detect E/1 and F/1 multiple faults masked » e.g. g/1 and E/1

Northeastern U N I V E R S I T Y 18 Testing Networks of AND, OR & INV Primary Inputs Inverting Block Non-Inverting Majority Voters U0 U1 Primary Outputs Control line Primary Inputs + Literals Push all inversions to the primary input level. An equivalent network of only AND and OR » take literals as inputs.

Northeastern U N I V E R S I T Y 19 Pushing Back Inversions A B C D Z A B C D D Z Push all inversion to the primary input A B C D D Z MV U0 U1 1 0 MV implementation

Northeastern U N I V E R S I T Y 20 QCA Manufacture Defects Manufacture consists of Synthesis and Deposition Defects in Synthesis part results in imperfect cells: » missing/extra dots; missing/extra electrons Defects in Deposition part results in cell misplacement: » cell displacement, misalignment, etc. Defect are much more likely to appear in the Deposition part * Personal correspondence with Prof. M. Lieberman in department of Chemistry and Biochemistry, University of Notre Dame

Northeastern U N I V E R S I T Y 21 Fault model Cell displacement: » defective cell is misplaced within original direction; Cell misalignment: » direction of defective cell is misplaced; Cell omission: » particular cell is missing compared to the defect-free design. Majority Voter Here we consider only cell misplacement faults caused in the deposition part.

Northeastern U N I V E R S I T Y 22 Synthesis Results Synthesis tool: Synopsis Design Compiler and Synopsis Library Compiler Synthesis results show that existing tools can not make efficient use of MV Note: AND2 and OR2 can be implemented with MV Majority Voter

Northeastern U N I V E R S I T Y 23 AOI (And-Or-Inverter) Gate Motivation » MV is not universal, doesn’t have INV function » Not favorable for synthesis by existing tools AOI gate » Universal complex gate, 7 cells » With embedded AND, OR and INV functions » Desirable for Synthesis » Arranged as two nested MVs

Northeastern U N I V E R S I T Y 24 Layout and Schematic F=MV(D,E,MV(A’,B,C’)) Two nested Majority Voters Cell B has stronger effect on device than other input cells; » therefore placed further than other inputs 25nm 35nm 20nm 5nm A B C MV1 D E F MV2 MV1 MV2 A B C D E F AOI Gate

Northeastern U N I V E R S I T Y 25 Wired AOI Gate AOI gate is stable Connect AOI gate to binary wire while preserving original logic function Place wires apart to reduce interference MV1 E MV2 D 20nm 5nm 25nm 35nm A B C B A C D E AOI Gate

Northeastern U N I V E R S I T Y 26 Properties Property 1. All input values are inverted output value is inverted; Property 2. Consider an arbitrary network of AOI gates with primary input vector V. If all bits are flipped, V V’,all nodes in network are flipped. Property 3. For any node in an arbitrary network of AOI gates, stuck-at-u fault is detected by input vector V stuck-at-u’ is detected by V’. AOI Gate

Northeastern U N I V E R S I T Y 27 Logic Functions AOI Gate AOI gate can be programmed into various 1-level and 2- level logic gates A B C MV D E F ORAND Gate A=0 D=0 NANDAND Gate B=1 D=0 B=1 D=0 E=0 NAND Gate A=0 D=1 E=0 NOTOR Gate (2-level) (1-level)

Northeastern U N I V E R S I T Y 28 Synthesis Results (I) Library consists of 8 two-level gates and 5 one-level gates derived from AOI gate Area (# of cells) improvement compared to synthesis results using MV and INV AOI Gate

Northeastern U N I V E R S I T Y 29 Synthesis Results (II) AOI Gate Library Consists of 8 two-level gates and 5 one-level gates derived from the AOI gate Gate count for each type of gates are shown Area (# of cells) improvement compared to synthesis results using MV and INV are shown

Northeastern U N I V E R S I T Y 30 Defect Characterization (I) AOI Gate Faulty AOI Gate: F=MV(B,D,E) Acts as a MV, Cell A and C has no effect on output 30nm 25nm A C E B D Input Cell B Displacement Fault 20nm 5nm Fault-Free AOI Gate: Cell size 20x20 sq.nm Dot size 5nm F=MV(MV(A’,B,C’),D,E) 25nm 35nm A C E B D

Northeastern U N I V E R S I T Y 31 Defect Characterization (II) AOI Gate Faulty AOI Gate: F=B Output determined by horizontal input B alone Input Cell B Displacement Fault 10nm 25nm A C E BD 20nm 5nm Fault-Free AOI Gate: Cell size 20x20 sq.nm Dot size 5nm F=MV(MV(A’,B,C’),D,E) 25nm 35nm A C BD

Northeastern U N I V E R S I T Y 32 Defect Characterization (III) Faulty AOI Gate: F=D’E’+(D’+E’)(A’B+BC’+A’B’C’) 30nm 15nm 25nm A C B D Output Cell Displacement Fault AOI Gate Fault-Free AOI Gate: Cell size 20x20 sq.nm Dot size 5nm F=MV(MV(A’,B,C’),D,E) 25nm 35nm A C B D 20nm 5nm

Northeastern U N I V E R S I T Y 33 Test Sets Test set with 100% coverage to detect all cell displacement defects: » only 2 vectors needed » ABCDE={00000,00001} Test set with 100% coverage to detect all PIN stuck-at faults: » 4 vectors needed » ABCDE={01110,00101,00000,00001} Test sets generated using PIN fault model can cover all internal structural faults, very useful in test vector generation AOI Gate

Northeastern U N I V E R S I T Y 34 Full Adder Full adder with MV, INV: » 3 MVs, 1 INV » 25 cells for active device AOI Gate AOI A B EC D F MV E D A B C Wired AOI gate F AOI A B EC D F abcin cout=a*b+b*cin+a*cin sum=a xor b xor cin Full adder with AOI: » 3 AOI gates » 14 cells for active device

Northeastern U N I V E R S I T Y 35 Future Research:Circuits Establish Electrical Model for QCA Design Sequential Modules in QCA Delay Faults due to Defects (Kink Effect) Interface Circuitry Between QCA and CMOS

Northeastern U N I V E R S I T Y 36 Future Research: Systems Develop QCA-Driven Synthesis Timing Characterization Across QCA Modules Cell Placement/Routing for Room Temperature Operation Pipeline Design for High Performance