DEVICES AND DESIGN : ASIC. DEFINITION Any IC other than a general purpose IC which contains the functionality of thousands of gates is usually called.

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Presentation transcript:

DEVICES AND DESIGN : ASIC

DEFINITION Any IC other than a general purpose IC which contains the functionality of thousands of gates is usually called an ASIC (Application Specific Integrated Circuit) AISCs are used in a wide variety of products ranging from consumer products such as video games, digital cameras, automobiles and personal computer, to high-end technology products such as workstations and supercomputers

Partition Floorplanning Placement DESIGN FLOW FROM 1 ST DAY Routing Extraction and Verification Front-end physical design Back-end

METHODOLOGY Design entry and analysis Technology optimization and floorplanning Design verification Layout

DESIGN ENTRY Describes the design’s intended function Written in English and then translated into a form that can be understood by the software Two principal methods – Hardware Description Languages – Schematic capture

DESIGN ENTRY EXAMPLES

DESIGN ANALYSIS Verify the functionality – Determine if the intended function is correctly implemented Done through simulation

TECHNOLOGY OPTIMIZATION Maps the technology independent description of a design to a library of logic circuits provided by an ASIC vendor Design is realized as a technology-dependent netlist that consists of a series of instances of circuits from the ASIC vendor’s library, interconnected in a manner to implement the functionality described in the previous view

FLOORPLANNING Floorplan is the physical description of the ASIC Mapping logical description to the physical description Involves physically placing logic groups on a die Objectives – To reduce area – To minimize timing

DESIGN VERIFICATION The design is resimulated to ensure that the design has not been corrupted by the synthesis process It is ensured that the design is functionally correct and meets physical requirements The design must produce the exact same functional results as the pre-synthesis version of the design, given the same set of stimulus

LAYOUT Placement – Standard cells location is defined to a particular position in a row – Space is set aside for interconnect to each logic/standard cell – Objectives Making the chip as dense as possible Minimize the total wire length Routing – Connecting various blocks on the chip with one another

LAYOUT

ASIC VENDOR SELECTION CRITERIA ASIC library content and characteristics Design turn-around-time Price of the die Power consumption Design methodology

TOP COMPANIES Synopsys Cadence Mentor Graphics

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