24/03/2010 TDAQ WG - CERN 1 LKr L0 trigger status report V. Bonaiuto, G. Carboni, L. Cesaroni, A. Fucci, G. Paoluzzi, A. Salamon, G. Salina, E. Santovetti, F. Sargeni

24/03/2010 TDAQ WG - CERN 2 L0 LKr trigger Use analog sums (2x8 cells) and all the cables already existing New pixel based trigger processor Low granularity readout independent from the full granularity readout Fast readout for software triggers read-out boards 13k analog channels analog sums LKr calorimeter DAQ 864 analog channels L0 LKr trigger read-out after L0 L0TS

24/03/2010 TDAQ WG - CERN 3 L0 Lkr trigger: architecture Concentrator TELL1: merging, sorting 8 Front-End TELL1 Front-End TELL1: pulse reconstruction (time, position and energy)‏ 32 analog channels (1 channel = 2x8 liquid krypton cells analog sum)‏ 1 analog sum (supercell) = 2x8 channels 28 FE TELL1s, 7 concentrator TELL1s, 32 supercells per TELL1

24/03/2010 TDAQ WG - CERN 4 FE boards: pulse reconstr (time, position, energy) ‏ L0 LKr Trigger: architecture Three new mezzanines: –FE + ADC mezzanine –TX mezzanine (custom link for the trigger + ethernet for the readout) – being designed –RX mezzanine (custom link for the trigger) – tested Two 9U crates! Depending on L0TS implementation a final TELL1 maybe will be needed channels for the readout  864 channels (2x8 pixel supercells) for the trigger! Concentrator boards: merging, sorting TELL1 28 boards L0TS FE+ADC M. 32 supercels TELL1 8 ch 7 boards 8 RX trig link 1-3 m copper 32 ch 2 Eth + 2 trig TX

24/03/2010 TDAQ WG - CERN 5 TELL1 NA62 RX mezzanine Four links per mezzanine, eight links per TELL1, 1-3 meters copper 6.4 Gbps 0.6 Gbps

24/03/2010 TDAQ WG - CERN 6 TELL1 NA62 RX mezzanine

24/03/2010 TDAQ WG - CERN 7 Test setup 2m copper cable RX mezzanine Development kit “Final” cable cut and rearranged to connect to the development kit

24/03/2010 TDAQ WG - CERN 8 Test setup Developed software and firmware to receive digital data on the TELL1 Control (enable, disable, ecc) the link and read data from the CCPC Pattern Generator -> National Semiconductors development board -> (2 meters) cable

24/03/2010 TDAQ WG - CERN 9 Test setup (2 meters) cable -> RX mezzanine -> PP0 FPGA on the TELL1 -> Logic Analyzer connector on the TELL1 -> Logic Analyzer

24/03/2010 TDAQ WG - CERN 10 Test result (PG/LA snapshot)‏

24/03/2010 TDAQ WG - CERN 11 Test result (PG/LA snapshot)‏

24/03/2010 TDAQ WG - CERN 12 Comment on cables 3M cable suggested by National Semiconductors At the moment for the test we bought the version of the cable assembly available on the market even if the connector is too big (few millimeters)‏ Got from 3M the quotation for a special version with a smaller connector (this new connector will not have the big screw of the existing ones, however is a standard 3M connector used in other cable assemblies)‏ Got from 3M 1 sample of the “final cable” (3 meters)‏ Minimum Order Quantity = 100 pcs of the same length

24/03/2010 TDAQ WG - CERN 13 ADC mezzanine test setup (on hold)‏

24/03/2010 TDAQ WG - CERN 14 ADC mezzanine test setup (on hold)‏ The technician working in our group (G. Paoluzzi) assembled the hardware for ADC tests Next step: simulated or measured data from the Arbitrary Waveform Generator -> received and digitized with the TELL1

24/03/2010 TDAQ WG - CERN 15 TELL1 components procurement Components for NA62 global TELL1 production (E. Santovetti) 100 CCPC + 80 RAM modules - 1 CCPC + 1 RAM: 300 CHF 320 TELL1 input connectors (4 per TELL1, 80 TELL1s) – 1 QSS FDA: 6.80 Euro 70 Intel 4-port Ethernet MAC (obsolete) + Marvell Ethernet transceiver (150 Euro) Material database on-line TELL1 test station A second TELL1 test station has been implemented to host the TELL1 boards for the production phase

24/03/2010 TDAQ WG - CERN 16 Requitements/caveat (TELL1++)‏ TELL1++: power consumption (and noise) should not increase – we will have 18 TELL1s per crate (like LHCb)‏ L0TS: L0 LKr output -> assuming a (very) conservative estimate for the output of 30 MHz hit x 64 bit word = 2 Gbps the L0TS must have an adequate input bandwidth for the L0 LKr (using a link at full bandwidth implies an increase in the average latency: OK for the readout but not for the trigger)‏ We are designing the TX (2 GBE + 2 trigger link) board After the TX board we will start the design of the interface with the Lkr readout system Requitements/caveat (TELL1++)‏ Requitements/caveat (Lkr interface)‏