PSI - 11 Feb The Trigger System of the MEG Experiment Marco Grassi INFN - Pisa On behalf of D. Nicolò F. Morsani S. Galeotti

PSI - 11 Feb Expected Trigger Rate Accidental background and Rejection obtained by applying cuts on the following variables photon energy photon direction hit on the positron counter time correlation positron-photon direction match The rate depends on R  R e +  R  2

PSI - 11 Feb The trigger implementation Digital approach –Flash analog-to-digital converters (FADC) –Field programmable gate array (FPGA) Final system  Only 2 different board types  Arranged in a tree structure on 3 layers  Connected with fast LVDS buses  Remote configuration/debugging capability Prototype board Check of:  the FADC-FPGA compatibility  chosen algorithms  synchronous operation  data transmission

PSI - 11 Feb Prototype board : Type 0 VME 6U A-to-D Conversion Trigger I/O –16 PMT signals –2 LVDS transmitters –4 in/2 out control signals Complete system test 2 boards 16 4 Type0 Trigger Start 4 LVDS Rec Sync Trigger Start FADC FPGA Control CPLD PMT x VME Sync Clock Sync Trigger Start 4 48 LVDS Trans 3 Out Analog receivers Spare in/out Board Type0

PSI - 11 Feb The board PMT inputs LVDS transm. LVDS receiv. FADC FPGA configuration EPROMS Differential drivers package error solved with a patch board control signals.

PSI - 11 Feb Prototype system Board 0Board 1 Ancillary board Clock, sync, trigger and start distribution LVDS connection Two identical Type0 boards

PSI - 11 Feb Prototype system configuration Diff. driver Fadc Proc. Algor. LVDS Rx LVDS Tx Proc. Algor. Circ. buff Circ. buff Circ. buff Circ. buff Diff. driver Fadc Proc. Algor. LVDS Rx LVDS Tx Proc. Algor. Circ. buff Circ. buff Circ. buff Circ. buff 16 PMT input output LVDS in final Board 1 Board 0

PSI - 11 Feb Prototype system tests Debugging of the first board Type0 in Pisa –A minor error fixed System assembled at PSI in Nov. ‘03 – 100MHz synchronous operation – Negligible transmission error rate – Satisfactory operation of the analog interface Connection with the Large Prototype –PMT from #0 to #31 –Collected data Alpha Led  0

PSI - 11 Feb Alpha Time [10 ns] Amplitude [mV] Input cyclic-buffer board 1

PSI - 11 Feb LED Time [10 ns] Amplitude [mV]

PSI - 11 Feb 00 Time [10 ns] Amplitude [mV]

PSI - 11 Feb Internal trigger Time [10 ns] Amplitude [mV] Max. Amplitude (  2) Index of Max Amplitude sum Pulse time Input cyclic-buffer board 0 Output cyclic-buffer board 0

PSI - 11 Feb LVDS transmission Time [10 ns] Amplitude [mV] Max. Amplitude (  2) Index of Max Amplitude sum Pulse time Output cyclic-buffer board 1 LVDS input cyclic-buffer board 0 7 clock cycles delay

PSI - 11 Feb  0 data Charge spectrum Only 32 PMT Example of data comparison

PSI - 11 Feb Further works Hardware –JTAG programming/debugging through VME by modifying the Type0 –Block transfer in A32D16 format (VME library to be modified) –Final characterization on linearity, cross talk … Analysis –Alpha, Led and  0 data to extensively check the algorithms Conclusions The prototype system met all requirements It is available to trigger the LP in future beam tests

PSI - 11 Feb Final system Trigger location: platform –Spy buffers to check the data flow are implemented –JTAG programming/debugging through VME: test planned with Type0 Final boards –VirtexII or Spartan3 ? Main FPGA XCV812E-8-FG900 is old, first production in 2000 –Connectors Analog input by 3M coaxial connectors LVDS connection by 3M cables –Differential driver on the trigger board Type1 –Other components are fixed: FADC, LVDS Tx and Rx, Clock distributor –Ancillary boards: distribution of control signals Design of final prototypes (Type1 and Type2) june 2004 –If tests are ok  start of the mass production –Estimated production and test 1 year

PSI - 11 Feb Full System Test Milestone AssemblyDesignManufactoring Prototype Board Final Prototype Jan 2002 Trigger now