Instructor: Yuzhuang Hu

Course Timetable Lectures: Wednesday 17:30-20:20, HCC 2510 Labs: Thursday 17:30-18:20, HCC 7050 Midterm, Final: TBA Office Hours: Instructor: Friday 14:30-16:30, HCC 2134 TA: TBA

Contact Information Instructor: Yuzhuang Hu Office Hours: Friday 2:30pm-4:30pm Office: HC 2134 Phone: TA: Zhiyong Lu Office Hours: TBA

Marking Scheme 4 Assignments + Labs, 30% Late Penalty: -20% per day Midterm, 20% Final, 50%

What is Computer Architecture? Instruction Set Architecture: the actual programmer visible instruction set. Implementation  Organization: high level aspects of a computer’s design.  Hardware: specifics of a machine, e.g., the detailed logic design.

A Personal Computer Screen Keyboard Hard drive Drive Controller Bus Interface RAM Processor Graphics Adapter CPU, FPU, MMU Internal Cache External Cache

Von Neumann Architecture Memory Input/Output Control Unit Data Path CPU Stored program concept.

Circuit Design Top-Down Approach: starting with the objective, finding some good way to break it down to simpler parts. Bottom-Up Approach: designing some low level circuits and building more complex components based on these circuits.

Binary Numbers Digital signals are in fact analog. 0 and 1 are represented by voltage ranges Time Voltage(Volts) 0 1 Time

Number Systems Decimal numbers are of base 10, e.g., 724 = 7 × × ×10 0 Binay numbers are of base 2, e.g., (1101) 2 = 1 × × × ×2 0 = 13

Convert a decimal number N to binary Loop remainder = N mod 2 add remainder to the left of the result N = N / 2 An example: result remainder 1 1 1

Full Adder A full adder considers a carry in bit. Truth Table of Full Adder Inputs X Y Z C S Outputs

Binary Subtraction Method 1: First compare the subtrahend with the minuend. Then subtract the smaller from the larger. Method 2: Directly subtract the subtrahend from the minuend. An example: Borrows into: Minuend: Subtrahend: Difference: Correct Difference:

Complements 2’s complement of a binary number M is defined to be the number 2 n – M. 1’s complement of a binary number M is defined to be the number (2 n – 1) – M. 1’s complement of M can be obtained by subtracting 1 each digit from 1. 2’s complement of M = 1’s complement of M + 1.

Subtraction Using 2s Complement Task: compute M – N, where M and N are two n-digit unsigned numbers.  Add the 2s complement of N to M. This performs M + (2 n – N) = M – N + 2 n.  If M ≥ N, discard the end carry, leaving M – N.  If M < N, the sum equals 2 n – (N – M). Do a correction by taking the 2s complement of the sum and place a minus sign in front.

Signed Numbers A binary number M can be represented by:  Signed-magnitude system: Add 0 to the left of M if M ≥ 0, and add 1 to the left of M if M < 0. For example, +7 = 0111, -7 =  Signed-complement system: Add 0 to the left of M if M ≥ 0, and add 1 to the left of the 2s complement of M if M < 0. For example, +7 = 0111, -7 = 1001.

Signed Binary Addition and Subtraction The subtraction of M – N under the signed- magnitude representation: similar to the unsigned subtraction using 2’s complements. The subtraction of M – N under the complement representation : obtained from the addition of the two numbers, including their sign bits. A carry out of the sign bit position is discarded. No comparison or subtraction is needed.

Signed Binary Subtraction contd. When M is positive, and N is negative: This performs M + 2 n + (2 n – N)=M – N + 2 n+1. If M - N ≥ 0, then the sign bit is 0 after discarding the carry. If M - N < 0, there is no carry out and the sign bit is 1. It can be similarly argued when M is negative, and N is positive

Pitfalls: Overflow! Overflow occurs when the sum takes more than n+1 bits. Two examples: An overflow condition can be detected by observing the carry into the sign bit position and the carry out of the sign bit position

Overflow Detection Logic An overflow occurs if the above mentioned two carries are not equal. N-bit Adder/Subtractor C n-1 CnCn C V

A Hardware Description Language: VHDL A hardware description language (HDL) is any computer language for formal description of digital logic and electronic circuits. HDL represents extensive parallel operations, whereas most programming languages represent serial operations. VHDL stands for VHSIC Hardware Description Language (Very-High-Speed Integrated Circuits).

Entity Declarations in VHDL entity full_addr is port ( c_in: instd_logic; x: instd_logic; y: instd_logic; c_out: outstd_logic; sum: outstd_logic ); end full_addr;

Describing Behaviour in VHDL architecture behav of full_addr is begin -- Your VHDL code defining the model c_out <= (x and y) or (x and c_in) or (y and c_in) after 2 ns; Sum <= x xor y xor c_in after 2 ns; end behav; Full Adder x y c_in c_out sum Truth Table of Full Adder Inputs X Y Z C S Outputs

Describing Structure in VHDL architecture structure of full_addr is signal s1, s2, s3:std_logic; Begin G1:xor_3 port map(INA=>c_in, INB=>x, INC=>y, Y=>sum); G2:and_2 port map(INA=>c_in,INB=>x, Y=>s1); G3:and_2 port map(INA=>x,INB=>y, Y=>s2); G4:and_2 port map(INA=>c_in,INB=>y, Y=>s3); G5:or_3 port map(INA=>s1,INB=>s2, INC=>s3,Y=>c_out); end structure ;

Signals in VHDL Signals are used in VHDL to interconnect components. Signals have propagation delays. They behave like some real wires. Each signal can have only one source.

Discrete Event Time Model We need to simulate VHDL programs to verify whether the models we built are correct. In a circuit digital signals change their values concurrently. VHDL simulates the passage of time of the signals in discrete events.

Concurrent Statements in VHDL Concurrent-Signal-Assignment Statements: sum <= x xor y xor c_in after 2 ns; Process-Statements: SUMPROC: process ( x, y, c_in) begin sum <= x xor y xor c_in after 2 ns; end process SUMPROC;

Concurrent Statements Contd. Component-Initiation-Statements: G1:xor_3 port map(INA=>c_in, INB=>x, INC=>y, y=>sum); An xor gate with 3 inputs would be instantiated, and its inputs would be wired with x, y, and c_in.

Signal Transactions and Events When a signal assignment occurs, VHDL will treat it as a transaction and schedule the real assignment in some later time. An event of a signal happens when the signal changes its value. t1t1 t1t1 t3t3 t3t3 t2t2 t2t2 t4t4 t4t4 t5t5 t5t5 0 ns 2 ns 4 ns

Some Examples of Generating Transactions The current time is 5ns, after executing S <= ‘0’ after 10ns; The transaction list would be: The current time is 16ns, after executing S <= ‘1’, ‘0’ after 10ns; The transaction list would be: ns ns 26 ns 0 0

Initialization Phase All signals are given initialization values. The simulation time is set to 0. All processes are executed until they suspend. When executing each signal assignment statement, a transaction on that signal will be generated.

A Simulation Cycle First Stage: the transactions with the earliest time will be removed from the list and executed. The simulation time will be forwarded to that time. Second Stage: when an event occurs in the first stage, all processes sensitive to the corresponding signal are executed. This means new transactions may be inserted to the list.

Test Bench A test bench is a VHDL program designed to test your entities. The entities will be instantiated in the test bench. An example: entity tb_fa is end tb_fa; architecture behav of tb_fa is signal x1, y1, c_in1, c_out1 :std_logic; begin x1 <= ‘0’; y1 <= ‘1’; c_in1 <= ‘0’; UUT: full_addr port map(x=>x1, y=>y1, c_in=>c_in1, c_out=>cout1); end behav;

Variables in VHDL The simulation cycles do not apply to variables in VHDL. As in any other programming language, the change on a variable after executing a statement is immediately effective. In contrast, assignments on signals are not immediately visible for later sequential statements. A pitfall: s1 <= ‘0’; ………….. if s1=‘0’ then ………….. It won’t give the answer you want.

THANKS!