Mark Raymond - 28/04/061 Trip-t and TFB status Trip-t schematics Trip-t operation at T2K SiPM connection and gain considerations Latest results from version 2 – the final version TFB conceptual layout interfaces components electronic calibration data volumes plans for this year

Mark Raymond - 28/04/062 Trip-t schematics - overview taken from Bench test of TRIP-t, Leo Bellantoni, Paul Rubinov, D0 note ##v4 select which group of 16 to output reset during preamp reset period trigger pipeline column prior to readout not used mux control signals programming interface serial analogue output 32 inputs not used

Mark Raymond - 28/04/063 Trip-t schematics – front end taken from Bench test of TRIP-t, Leo Bellantoni, Paul Rubinov, D0 note ##v4 don’t use x10 set to zero to avoid linearity discontinuity not used preamp disc. thresh to pipeline

Mark Raymond - 28/04/064 The proposed mode of Trip-t operation for beam spill data acquisition is as follows during spill integrate signal for each bunch and store result in pipeline* (15 timeslices for 15 bunches) timestamp high gain channel discriminator outputs that fire and store after spill continue running in same way, for a while, to catch late signals (  decay) readout entire contents of pipeline assemble data block containing hit timestamps and all digitized analogue data and transmit transmitting all info in this way allows histogramming of single p.e. events to monitor SiPM gain vast majority of data is pedestal + single/double p.e. hits only Trip-t operation at T2K 5.25  s spill period 2.8  s after spill active period 74  s (23 cell) readout period (if O/P mux running at 10 MHz) start of spill end of spill at this time trip-t switches to inter-spill operational mode (cosmic trigger) *Note: pipeline operated using 2 timeslices/preamp integration period to avoid FIFO overflow problem, so pipeline length reduced to 24 (explained in

Mark Raymond - 28/04/065 SiPM connection HV(TFB) 1 M  50  thin coax SiPM trip-t 100pF 10pF short length (~20 cm) coax between SiPM and tript SiPM connected between core and coax sheath (core carries bias voltage) 50  provides some kind of termination for the cable charge split between two tript channels using different capacitor values to get high/low gain 330pF HVtrim

Mark Raymond - 28/04/066 Gain considerations don’t know what final SiPM gain will be, but assume production devices will be quite well matched in any case will have individual channel gain adjustment by HVtrimDACs Signal shared between Cadd, Chi and Clo (also some strays) Choose Cadd to match final SiPM gain (330pF about right for 5x10 5 ) Cadd also helps with gain discontinuity when hi gain channel saturates (see HV(TFB) 1 M  50  thin coax SiPM trip-t Chi 100pF Clo 10pF Cadd 330pF HVtrim

Mark Raymond - 28/04/067 Gain ratio considerations aim for fullscale signal capability (logain channel) of 500 p.e. (e.g. 40 pC for 5x10 5 SiPM gain) let’s assume want discriminator threshold adjustment range 0 – 5 p.e. trade-off between range and threshold adjustment precision here (see fixed x10 gain stage between preamp and comparator means higain fullscale ~ 50 p.e. so hi:lo gain ratio 10:1 x10 1pF reset Vth disc. O/P analogue pipeline Qin HV(TFB) 1 M  50  thin coax SiPM trip-t Chi 100pF Clo 10pF Cadd 330pF HVtrim

Mark Raymond - 28/04/068 Latest Trip-t test results from final version Trip-t Programmable Digital Pattern Generator ~14 control lines preamp int./reset pipeline, multiplexer, programming Qinj ADC Scope LabVIEW VME ck and trig. level shift dECL -> 2.5V CMOS prog. attenuator

Mark Raymond - 28/04/069 Photos Trip-t board dECL -> 2.5 V CMOS level shift digital pattern generator dECL outputs ADC

Mark Raymond - 28/04/0610 Tript V1 v. V2 linearity version 2 linearity better but still some gain reduction for small signals => will need calibration

Mark Raymond - 28/04/0611 Tript V2 linearity all 16 channels, hi and lo gains component values as on p. 6/7 lo gain saturates at ~ 40 pC hi gain saturates at ~ 4 pC

Mark Raymond - 28/04/0612 Tript V2 linearity log-log plot of same data 10:1 gain ratio means gain range change occurs where logain signal size already large so no S/N problems

Mark Raymond - 28/04/0613 Tript V2 discriminator measurement count the no. of times the discriminator fires for 1000 preamp integration periods sweep the injected signal size for 5x10 5 1p.e. -> 0.08 pC pk-pk width ~ 1 p.e. also for this measurment so +/- 0.5 p.e. precision can improve but trade-off with adjustment range 1 p.e. discriminator curves for all 16 higain channels

Mark Raymond - 28/04/0614 Tript V2 discriminator timewalk 1 p.e. = 80 fC large timewalk and chan-to-chan spread for small signals OK for signals > ~ 3 p.e. could improve but once again trade-off with discriminator adjustment range

Mark Raymond - 28/04/0615 SiPM/tript version 2 results Russian SiPM (CPTA – 600 pixels) 39 V bias led pulsed during preamp integrate period -> red distribution preamp integrate:reset ratio 325ns:75ns get blue distribution when led switched off -> can see 1 and 2 p.e. peaks higain channel

Mark Raymond - 28/04/0616 HVtrim cal dac HVtrim cal dac 16 x SiPM connectors powerFE-FPGA local supply and T monito- ring DAQ I/F trip-t ADC TFB – Trip-t Front end Board picture shows conceptual layout of main components real layout only just beginning on analogue front end interface need to keep component density high here and take care of signals propose to use ultra-min. coax connectors SiPM connection needs thought this picture is conceptual – reality will be different – but we need to decide what the reality should be in the near future need to consider cable routing, how connections can be made, cooling … aiming for 10 cm x 15 cm

Mark Raymond - 28/04/0617 Trip-t pinout

Mark Raymond - 28/04/0618 Trip-t control signals Programming interface and O/P mux control PrgReset resets programming interface PrgCtrl defines whether programming the chip or running the output MUX PrgIn serial programming info or MUX reset (depending on PrgCtrl) PrgOut serial output to read back programmed register values PrgClk shift in serial programming data or MUX clock (depending on PrgCtrl) Pipeline control and triggering PlnResetResets the pipeline PlnClkPipeline clock SkipBTriggers the pipeline (stops timeslice of interest being overwritten) PR1Initiates pipeline readout (validated by PlnClk edge) MoveDataClears triggered pipeline column (allows timeslice to be overwritten – validated by PlnClk edge) Preamp integrate/reset cycling PreResetSwitches preamplifiers between integrate/reset Pre2aReset complement of PreReset Pre2bReset complement of PreReset Discriminator outputs enable and reset DigenLenables one bank of 16 discriminator outputs off-chip (fixed level) DigenUenables the other bank (fixed level) DigResetBresets the discriminators (do this during preamp reset period) some dual functionality here 14 – 16 control lines depending on whether we fix DigenL/DigenU or leave programmable

Mark Raymond - 28/04/0619 Trip-t registers serial programming interface chip ID: register address: 5 bits operation: 3 bits (read/write/set/reset/default) 1 bit space value: 8/10/34 bits ~ 300 bits to send to fully program chip so for 50k channels, ~3000 trip-t’s need ~ 900k bits (not that much)  initialising the system from scratch will not take any significant time

Mark Raymond - 28/04/0620 ADC D0 uses AD9201 – seems suitable for us too dual channel, 20 MHz, 10-bit, single supply (2.7 V min.) parallel O/P but 2 channels data multiplexed onto single 10-bit bus 215 mW (+3V supply) HVtrimDAC propose AD channel (2/trip-t), buffered outputs, single supply (2.5V min.) serial load 8 bits res’n (could use 10 or 12 bit versions) ADC and HVtrimDAC propose to prototype the use of these chips in conjunction with trip-t test board before committing to TFB layout

Mark Raymond - 28/04/0621 TRIP-T 16 SiPM’s 16 disc.O/P’s 14 control 4 cal lines HVtrim 4 HVtrim control (2 HVtrimDACs) 10 bits 2 ADC control TRIP-T 16 SiPM’s 16 disc.O/P’s 14 control 4 cal lines HVtrim FE-FPGA digital IO per pair of Trip-T’s (( )x2) + 12 = 88 assuming all control lines independent (some could be shared between trip-t’s but would lead to more complicated pcb track routing) 4 Trip-t’s per TFB => 176 total more lines required for: local T and supply voltage monitoring cal level generation off-board communication ….. 4 HVtrim control (2 HVtrimDACs) TFB Trip-t I/O

Mark Raymond - 28/04/0622 propose something like electronic chain calibration Vcal (need another DAC here) to 16 trip-t SiPM channels before gain splitting capacitors every 4 th channel from FE-FPGA needs to be prototyped – provision to do this included on trip-t test board

Mark Raymond - 28/04/0623 TFB interfaces 4 LVDS pairs Clocks input:100 MHz, 1Hz, Spill/Cosmic trigger Data inputprogramming setup (trip-t, HVtrim, CAL levels) Data outputread back, spill data, cosmic trigger out, monitoring data, … RF clocksynchronization to beam Power SiPM HV +2.5 (tript, HVtrimDACs and FPGA) +3.3 (ADC, FPGA) other levels may be necessary?

Mark Raymond - 28/04/0624 for programming tript: ~ 900 kbits for 50k channels HVtrim DACs: 8 bits res’n x 50k chans = 400 kbits for raw spill data readout (data only) assume 23 integration periods 4 tript’s / TFB 32 channels/tript (hi and logain) 10 bit ADC => ~30k bits /TFB /spill + hit timestamp data and associated hit channel addresses some data volume numbers

Mark Raymond - 28/04/0625 Clock and trigger recovery and synchronization MHz / RF clock / spill trigger / cosmic trigger Tript register programming SiPM HV-trim - individual HV trim DACs on all SiPM channels need programming Tript and ADC operation sequencing during spill - digital control signals for integrate/reset, pipeline write cycling, pipeline read, output mux cycling and ADC control and readout Hit timestamping (linked to above) - timestamp tript discriminator outputs to 2.5 ns precision Data formatting and transmission - bundle up timestamp information and digitized analogue data into agreed fromat and transmit Cosmic trigger formation - during spill gaps (~ 3 secs) need to cycle chip, look for patterns of discriminator hits from neighbouring channels, transmit trigger off-board, respond with data if trigger returned local monitoring – temperature, local voltage levels electronic calibration – outside normal physics data taking TFB FE-FPGA tasks

Mark Raymond - 28/04/0626 plans for this year complete tests with trip-t test board calibration cct ADC HVtrimDAC other things to define what to monitor locally and how to implement it 1 st TFB prototype to be produced by October in parallel produce firmware to implement main functionality detailed electrical characterization by end of year