Solar Probe Plus FIELDS DFB Report Quarterly Management July 18, 2013

SPP Fields DFB DFB Science: Finalized Sensor inputs; gain states, band-pass (except SCM – in process) Defined: Coordinated Burst implementation, Digital Burst Memory (size & no of buffers and channels), Spectra and Cross-Spectra DFB Prototype: Prototype design complete, layout review Tues 7/16, quick turn fab planned All FPGA modules for prototype bring-up complete Board will be used for most of early development and then for testing/characterization of Sidecar ASICs after moving to ETU board DFB ETU: Schematic in process for Xilinx FPGA Daughter Card FPGA development status shown in separate slides DFB Flight: Received Sidecar ASICs; EIDP/workmanship deviation released this week, risk added Continued EEE parts submittal to PCB for approval, no known issues at this time SPP Quarterly Review 7/18/13

Likelihood of Occurrence (probability) Consequence of Occurrence (Impact) HighMediumLow (Criticality) P = Performance C = Cost S = Schedule M = Mass IDTITLEPICritRetire At FF-DFB01Sidecar workmanship23 L Post PDR characterization testing F-DFB01 PM SPP Quarterly Review 7/18/13 If the Sidecar experiences latent failure and/or has reliability issues, then the lack of a complete EIDP and respective workmanship could hinder the debug/troubleshooting, and have the potential to degrade performance and warrant possible redesign which could increase needed mass and power. Risk mitigation plan is to perform characterization and environmental testing on Sidecars. These parts have prior electrical burn-in testing hence characterization and environmental tests will demonstrate good rigor to retire the risk. Risk rating: Probability 2, Impact 3; not likely to occur based on successful burn-in testing completed by vendor [GSFC/Teledyne]; consequences slightly higher based on possibility of reverting to backup plan of discrete ADCs. Proposed/heritage ADCs are not as rad-tolerant, require more board space (mass increases), more power, and/or could drive science return. Newer, more viable, ADCs identified but require radiation testing. DFB Sidecar Risk

DFB Block Diagram 4 SPP Quarterly Review 7/18/13

DFB FPGA Architecture SPP Quarterly Review 7/18/13

DFB FPGA Development Status 6 SPP Quarterly Review 7/18/13 7/18/13 Module NameVHDL CodeSimulationLab Testing Top Level Module100%0% SIDECAR ASIC Interface100%60%0% Mid-Freq Filters100%25%0% Low-Freq Filters100%25%0% Triggers100%0% Waveform Player75%0% Digital Burst Memory (DBM) [Prototype]100%0% Digital Burst memory (DBM) [Flight]0% Spectra/Cross-Spectra50%0% SDRAM controller fpr DBM50%0% SRAM controller for Spectra/Cross-Spectra100%20%0% SRAM controller for Data Processor100%20%0% Command Processor75%20%0% Data Processor (CCSDS packetizer, data compression) 50%0% SCM Calibration Signal Generator0% Simulation Testbench20%10%0%