ILP-Based Inter-Die Routing for 3D ICs Chia-Jen Chang, Pao-Jen Huang, Tai-Chen Chen, and Chien-Nan Jimmy Liu Department of Electrical Engineering, National Central University, Taiwan ASPDAC 2011

Outline Introduction Problem formulation Algorithms Experimental results Conclusions

Introduction 3D ICs are the promising way to get better performance, etc.  Good for SoC and SiP But the routing between dies has to be made

Introduction (cont.) Key issue: Routing interface between silicon-based layers and routing layers of 3D ICs  TSV and micro bump are popular Sometimes, we cannot control placement and routing on each die  Like IP reuse prompt dies, etc.  Re-Distribution Layer (RDL) is used

Schematic view

Previous works [7] address the freely assigned problem by network flow based alg.  Inexact connection [8] considers chip-package co-design  Still the inexact connection [9] are based on ILP  Terminals and bump pads are regular- distributed

Problem formulation M = {m 1, m 2,…,m |M| }: the set of all micro bumps. U = {u 1, u 2,…,u |N| }: the set of terminals in the upper die. B = {b 1, b 2,…,b |N| }: the set of terminals in the lower die. N = {n 1, n 2,…,n |N| }: the set of nets where each net n i defines the connection

Problem formulation (cont.) The inter-die routing problem for 3D ICs is to connect a set of uU and a set of b B through micro bumps mM such that no wire crossing in the upper and lower RDLs and the total wirelength is minimized under the 100% routability guarantee.

Assumptions Only one RDL routing layer  Lower cost Only one micro-bump for each net between two adjacent dies  Lower loading capacitance -> higher performance Freely assigned micro-bump

Algorithms Two stages  Micro-bump assignment  Non-regular RDL routing Determine the micro-bump location first, then do single-layer routing Both by ILP

Micro-bump assignment Objective  Maximize the number of micro-bump assignment for each net between two adjacent dies Constraints  Avoid detour – assign it in the bonding box of a net  Avoid edge crossing

Suitable assignment result

Unsuitable assignment result

ILP formulation for micro- bump assignment <- Maximize the assignment number (1) is for “One net chooses at most one micro-bump” (2) is for “One micro-bump chosen by at most one net” (3) is for “In upper RDL, if two edges cross each other, at most one can exist” (4) is for “In lower RDL, if two edges cross each other, at most one can exist”

Non-regular RDL routing Objective  Minimize wirelength Constraints - 100% routability  No congestion overflow  No edge crossing

Non-regular RDL routing (cont.)

Composes the terminals and micro- bumps according to their y-coordinates.  Source is lower one while target is the higher one for each pair. Adds ILP nodes as candidate nodes for net passing through and constructs candidate segments (edges). Solve by ILP

ILP formulation for non-regular RDL routing <- Minimize the total wirelength (1)is for “avoid congestion overflow in a horizontal interval” (2)(3) are for “one edge of the source (target) terminal of a net should be chose” (4) is for flow conservation (5) is for no edge crossing

ILP formulation for non-regular RDL routing (cont.) Some nets cannot be routed after the ILP reduction  Apply maze routing to find global routing path for those nets

Experimental results Environment  Implemented in C++  Linux with 2.2GHz AMD Opteron and 8GB memory Solver  lp_solve Benchmark  Real industry designs with pre-defined net-list and wire-width constraints

Benchmark information Since all cases achieve 100% routability, two experiments are applied to show the effectiveness

Effects of the reduction technique

Effects of micro-bump assignment The one without micro-bump assignment select the micro bump which is closest to the center of the bounding box for each net

Conclusions Proposes an inter-die routing algorithm for 3D ICs based on ILP Micro-bump assignment followed by non-regular RDL routing Experimental results shows that the proposed approach can obtain optimal WL and achieve 100% routability under reasonable CPU times