EE141 © Digital Integrated Circuits 2nd Inverter 1 Digital Integrated Circuits A Design Perspective The Inverter Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic July 30, 2002

EE141 © Digital Integrated Circuits 2nd Inverter 2 The CMOS Inverter: A First Glance

EE141 © Digital Integrated Circuits 2nd Inverter 3 CMOS Inverters Polysilicon In Out Metal1 V DD GND PMOS NMOS 2

EE141 © Digital Integrated Circuits 2nd Inverter 4 Voltage Transfer Characteristic

EE141 © Digital Integrated Circuits 2nd Inverter 5 CMOS Inverter VTC

EE141 © Digital Integrated Circuits 2nd Inverter 6 Switching Threshold as a function of Transistor Ratio M V (V) W p /W n

EE141 © Digital Integrated Circuits 2nd Inverter 7 Impact of Process Variations V in (V) V out (V) Good PMOS Bad NMOS Good NMOS Bad PMOS Nominal

EE141 © Digital Integrated Circuits 2nd Inverter 8 Propagation Delay

EE141 © Digital Integrated Circuits 2nd Inverter 9 CMOS Inverter Propagation Delay Approach 1

EE141 © Digital Integrated Circuits 2nd Inverter 10 CMOS Inverter Propagation Delay Approach 2

EE141 © Digital Integrated Circuits 2nd Inverter 11 Transient Response t p = 0.69 C L (R eqn +R eqp )/2 ? t pLH t pHL

EE141 © Digital Integrated Circuits 2nd Inverter 12 Design for Performance  Keep capacitances small  Increase transistor sizes  watch out for self-loading!  Increase V DD (????)

EE141 © Digital Integrated Circuits 2nd Inverter 13 Delay as a function of V DD

EE141 © Digital Integrated Circuits 2nd Inverter 14 Device Sizing (for fixed load) Self-loading effect: Intrinsic capacitances dominate

EE141 © Digital Integrated Circuits 2nd Inverter 15 NMOS/PMOS ratio tpLH tpHL tp  = W p /W n

EE141 © Digital Integrated Circuits 2nd Inverter 16 Inverter Sizing

EE141 © Digital Integrated Circuits 2nd Inverter 17 Inverter Chain CLCL If C L is given: - How many stages are needed to minimize the delay? - How to size the inverters? May need some additional constraints. In Out

EE141 © Digital Integrated Circuits 2nd Inverter 18 Delay Formula C int =  C gin with   1 f = C L /C gin - effective fanout R = R unit /W ; C int =WC unit t p0 = 0.69R unit C unit

EE141 © Digital Integrated Circuits 2nd Inverter 19 Apply to Inverter Chain CLCL InOut 12N t p = t p1 + t p2 + …+ t pN

EE141 © Digital Integrated Circuits 2nd Inverter 20 Optimal Tapering for Given N Delay equation has N - 1 unknowns, C gin,2 – C gin,N Minimize the delay, find N - 1 partial derivatives Result: C gin,j+1 /C gin,j = C gin,j /C gin,j-1 Size of each stage is the geometric mean of two neighbors - each stage has the same effective fanout (C out /C in ) - each stage has the same delay

EE141 © Digital Integrated Circuits 2nd Inverter 21 Optimum Delay and Number of Stages When each stage is sized by f and has same eff. fanout f: Minimum path delay Effective fanout of each stage:

EE141 © Digital Integrated Circuits 2nd Inverter 22 Example C L = 8 C 1 In Out C1C1 1ff2f2 C L /C 1 has to be evenly distributed across N = 3 stages:

EE141 © Digital Integrated Circuits 2nd Inverter 23 Optimum Number of Stages For a given load, C L and given input capacitance C in Find optimal sizing f For  = 0, f = e, N = lnF

EE141 © Digital Integrated Circuits 2nd Inverter 24 Optimum Effective Fanout f Optimum f for given process defined by  f opt = 3.6 for  =1

EE141 © Digital Integrated Circuits 2nd Inverter 25 Impact of Self-Loading on tp No Self-Loading,  =0 With Self-Loading  =1

EE141 © Digital Integrated Circuits 2nd Inverter 26 Normalized delay function of F

EE141 © Digital Integrated Circuits 2nd Inverter 27 Buffer Design Nft p

EE141 © Digital Integrated Circuits 2nd Inverter 28 Power Dissipation

EE141 © Digital Integrated Circuits 2nd Inverter 29 Where Does Power Go in CMOS?

EE141 © Digital Integrated Circuits 2nd Inverter 30 Dynamic Power Dissipation Energy/transition = C L * V dd 2 Power = Energy/transition *f =C L * V dd 2 * f Need to reduce C L, V dd, andf to reduce power. VinVout C L Vdd Not a function of transistor sizes!

EE141 © Digital Integrated Circuits 2nd Inverter 31 Modification for Circuits with Reduced Swing

EE141 © Digital Integrated Circuits 2nd Inverter 32 Adiabatic Charging 2 2 2

EE141 © Digital Integrated Circuits 2nd Inverter 33 Adiabatic Charging

EE141 © Digital Integrated Circuits 2nd Inverter 34 Node Transition Activity and Power

EE141 © Digital Integrated Circuits 2nd Inverter 35 Transistor Sizing for Minimum Energy  Goal: Minimize Energy of whole circuit  Design parameters: f and V DD  tp  tpref of circuit with f=1 and V DD =V ref

EE141 © Digital Integrated Circuits 2nd Inverter 36 Transistor Sizing (2)  Performance Constraint (  =1)  Energy for single Transition

EE141 © Digital Integrated Circuits 2nd Inverter 37 Transistor Sizing (3) F = V DD = f (f) E/E ref = f (f)

EE141 © Digital Integrated Circuits 2nd Inverter 38 Short Circuit Currents

EE141 © Digital Integrated Circuits 2nd Inverter 39 How to keep Short-Circuit Currents Low? Short circuit current goes to zero if t fall >> t rise, but can’t do this for cascade logic, so...

EE141 © Digital Integrated Circuits 2nd Inverter 40 Minimizing Short-Circuit Power Vdd =1.5 Vdd =2.5 Vdd =3.3

EE141 © Digital Integrated Circuits 2nd Inverter 41 Leakage Sub-threshold current one of most compelling issues in low-energy circuit design!

EE141 © Digital Integrated Circuits 2nd Inverter 42 Reverse-Biased Diode Leakage JS = pA/  m2 at 25 deg C for 0.25  m CMOS JS doubles for every 9 deg C!

EE141 © Digital Integrated Circuits 2nd Inverter 43 Subthreshold Leakage Component

EE141 © Digital Integrated Circuits 2nd Inverter 44 Static Power Consumption Wasted energy … Should be avoided in almost all cases, but could help reducing energy in others (e.g. sense amps)

EE141 © Digital Integrated Circuits 2nd Inverter 45 Principles for Power Reduction  Prime choice: Reduce voltage!  Recent years have seen an acceleration in supply voltage reduction  Design at very low voltages still open question (0.6 … 0.9 V by 2010!)  Reduce switching activity  Reduce physical capacitance  Device Sizing: for F=20 –f opt (energy)=3.53, f opt (performance)=4.47