Low Resistance Strip Sensors – RD50 Common Project – RD50/ CNM (Barcelona), SCIPP (Santa Cruz), IFIC (Valencia) Contact person: Miguel Ullán

Miguel Ullán (CNM-Barcelona) RD50 meeting (CERN) – Nov Outline  Motivation  Technological challenges  Preliminary experiments  Designs  Status and plan  Summary

Miguel Ullán (CNM-Barcelona) RD50 meeting (CERN) – Nov Motivation  In the scenario of a beam loss, a large charge deposition in the sensor bulk can lead to a local field collapse.  A conducting path to backplane is created and implant strip potential could reach a significant voltage.  Coupling capacitors can get damaged by the voltage difference between the implant and the readout strip They are typically qualified to 100 V  Punch-Through Protection (PTP) structures  used at strip end to develop low impedance to the bias line  Reduce distance from implant to bias ring  Placement of the resistor between the implant and bias rail (“transistor effect”). Micron HPK

Miguel Ullán (CNM-Barcelona) RD50 meeting (CERN) – Nov PTP effectiveness at ‘far’ end  Measurements with a large charge injected by a laser pulse showed that the strips can still be damaged  The voltages on the opposite end of the strip keep rising well above the 100V objective  The large value of the implant resistance effectively isolates the “far” end of the strip from the PT structure leading to the large voltages 4 Near end, plateau for PT structures Opposite end, no plateau. C. Betancourt, et al. “Updates on Punch- through Protection” ATLAS Upgrade week, Oxford, March 31, 2011.

Miguel Ullán (CNM-Barcelona) RD50 meeting (CERN) – Nov Proposed solution  To reduce the resistance of the strips on the silicon sensor.  A desired target value is 1.5 kOhm/cm (~ 1 order of magnitude reduction)  Not possible to increase implant doping to significantly lower the resistance. Solid solubility limit of the dopant in silicon + practical technological limits (~ 1 x cm -3 )  Alternative: deposition of Aluminum on top of the implant:  R □ (Al) ~ 0.04  /□  20  /cm Cross section Longitudinal section Top view

Miguel Ullán (CNM-Barcelona) RD50 meeting (CERN) – Nov Technological challenges  Metal layer deposition before the coupling capacitance is defined  2 metals processing  A layer of high-quality oxide/nitride with metal strips on top to implement the AC-coupled sensor readout (MIM cap).  Deposited (not grown)  Low temperature processing  PTP structure  Not tried before at CNM  Very dependent on surface effects (difficult to simulate)

Miguel Ullán (CNM-Barcelona) RD50 meeting (CERN) – Nov Metal on strip  Metal layer deposition on top of the implant before the coupling capacitance is defined.  MIM capacitors  Low temperature deposited isolation –PECVD ( ºC) –Risk of pinholes (Yield, Breakdown) –> 50 pF  ~ 3000 Å  Alternatives (for high T deposition) –Polysilicon + TaSi (tantalum silicide) –Tungsten  Experiments already performed at CNM on smaller dimensions. More experiments needed.

Miguel Ullán (CNM-Barcelona) RD50 meeting (CERN) – Nov Preliminary experiments  6 wafers batch of MIM capacitors  Different sizes –C1: 1100 x 1100  m 2 = 1.20 mm 2 –C2: 600 x 600  m 2 = 0.36 mm 2 –C3: 300 x 300  m 2 = 0.09 mm 2 –… (short strips ~ 0.5 mm 2 )  Low-temperature deposited isolation  PECVD ( ºC)  Use of a multi-layer to avoid pinholes  3 technological options:  Op1: 3000 Å of SiH 4 -based silicon oxide (SiO 2 ) deposited in 2 steps  Op2: 3000 Å of TEOS-based oxide deposited in 2 steps (Tetra-Etil Orto-Silicate)  Op3: 1200 Å Å Å of TEOS-based ox. + Si 3 N 4 + SiH 4 -based ox.

Miguel Ullán (CNM-Barcelona) RD50 meeting (CERN) – Nov MIM results  All 3 options give good MIM capacitors  Yield is high even for the largest caps (> 1 mm 2 ) (Not yet large statistics from all the wafers)  I-V meas: I LEAK < 3 20 V for the largest cap (C1)  Capacitance:  C(op1) = 122 pF/mm 2  C(op2) = 120 pF/mm 2  C(op3) = 110 pF/mm 2  Breakdown:  VBD(op1)| C1 = 170 V  VBD(op2)| C1 = 150 V (low statistics)  VBD(op3)| C1 = 210 V (low statistics)

Miguel Ullán (CNM-Barcelona) RD50 meeting (CERN) – Nov PTP design  Reduce implant distance to bias ring to favor punch-through effect at low voltages  Placement of the resistor between the implant and bias rail (“transistor effect”).  Compromise between PT effect and breakdown  Design of experiments varying d, p, n (2 indep. variables)  Simulations ? d s p Bias rail Polysilicon “bridge/gate” Implant

Miguel Ullán (CNM-Barcelona) RD50 meeting (CERN) – Nov Test structures  Test structure to measure voltage in the implant under laser injection at different strip distances  Laser tests (SCIPP-Santa Cruz)

Miguel Ullán (CNM-Barcelona) RD50 meeting (CERN) – Nov Wafer mask design  DOE for the PT structure  Control structures with standard resistive implant structure  Test structures  Extra structures for “slim edges”

Miguel Ullán (CNM-Barcelona) RD50 meeting (CERN) – Nov Status and Plan  Final measurements (more statistics) on MIM experiement wafers  DOE being planned and test structures designed  Final technological options being defined  Finish designs by end of January 2012  Fabrication (4-5 months): June 2012  Device electrical characterization, PTP validation, laser tests, Irradiation, re-characterization, post-irrad laser tests…

Miguel Ullán (CNM-Barcelona) RD50 meeting (CERN) – Nov Summary  RD50 Common Project: Low Resistance Strip Sensors (June 2011)  CNM-Barcelona, SCIPP-Santa Cruz, IFIC-Valencia  Reduced resistivity of the strip:  Proposed metal layer on top of the strip implant  MiM coupling capacitor  PTP structures implemented  Preliminary experiments on MIM coupling capacitors:  Good results (yield, large area, I LEAK, C, V BD ). More statistics needed  Options to be chosen  DOE on PT structures implemented  Final designs, start fabrication ~January 2012  Samples ~June 2012  This could be a very innovative solution for new generations of long-strip detectors and with great applications in future HEP experiments. 14