Modern VLSI Design 4e: Chapter 3 Copyright  2008 Wayne Wolf Topics n Wire delay. n Buffer insertion. n Crosstalk. n Inductive interconnect. n Switch logic.

Modern VLSI Design 4e: Chapter 3 Copyright  2008 Wayne Wolf Wire delay n Wires have parasitic resistance, capacitance. n Parasitics start to dominate in deep- submicron wires. n Distributed RC introduces time of flight along wire into gate-to-gate delay.

Modern VLSI Design 4e: Chapter 3 Copyright  2008 Wayne Wolf RC transmission line n Assumes that dominant capacitive coupling is to ground, inductance can be ignored. n Elemental values are r i, c i.

Modern VLSI Design 4e: Chapter 3 Copyright  2008 Wayne Wolf Elmore delay n Elmore defined delay through linear network as the first moment of the network impulse response.

Modern VLSI Design 4e: Chapter 3 Copyright  2008 Wayne Wolf RC Elmore delay n Can be computed as sum of sections:  E =  r(n - i)c = 0.5 rcn(n-1) n Resistor r i must charge all downstream capacitors. n Delay grows as square of wire length. n Minimizing rc product minimizes growth of delay with increasing wire length.

Modern VLSI Design 4e: Chapter 3 Copyright  2008 Wayne Wolf RC transmission lines n More complex analysis. n Step response: –V(t)    exp   t  RC .

Modern VLSI Design 4e: Chapter 3 Copyright  2008 Wayne Wolf Wire sizing n Wire length is determined by layout architecture, but we can choose wire width to minimize delay. n Wire width can vary with distance from driver to adjust the resistance which drives downstream capacitance.

Modern VLSI Design 4e: Chapter 3 Copyright  2008 Wayne Wolf Optimal wiresizing n Wire with minimum delay has an exponential taper. n Optimal tapering improves delay by about 8%.

Modern VLSI Design 4e: Chapter 3 Copyright  2008 Wayne Wolf Approximate tapering Can approximate optimal tapering with a few rectangular segments.

Modern VLSI Design 4e: Chapter 3 Copyright  2008 Wayne Wolf Tapering of wiring trees Different branches of tree can be set to different lengths to optimize delay. source sink 1 sink 2

Modern VLSI Design 4e: Chapter 3 Copyright  2008 Wayne Wolf Spanning tree A spanning tree has segments that go directly between sources and sinks. source sink 1 sink 2

Modern VLSI Design 4e: Chapter 3 Copyright  2008 Wayne Wolf Steiner tree A Steiner point is an intermediate point for the creation of new branches. source sink 1 sink 2 Steiner point

Modern VLSI Design 4e: Chapter 3 Copyright  2008 Wayne Wolf RC trees Generalization of RC transmission line.

Modern VLSI Design 4e: Chapter 3 Copyright  2008 Wayne Wolf Buffer insertion in RC transmission lines n Assume RC transmission line. n Assume R 0 is driver’s resistance, C 0 is driver’s input capacitance. n Want to divide line into k sections of length l. Each buffer is of size h.

Modern VLSI Design 4e: Chapter 3 Copyright  2008 Wayne Wolf Buffer insertion analysis n Assume h = 1: –k = sqrt{(0.4 R int C int )/(0.7R 0 C 0 )} n Assume arbitrary h: –k = sqrt{(0.4 R int C int )/(0.7R 0 C 0 )} –h = sqrt{(R 0 C int )/(R int C 0 )} –T 50% = 2.5 sqrt{R 0 C 0 R int C int }

Modern VLSI Design 4e: Chapter 3 Copyright  2008 Wayne Wolf Buffer insertion example Minimum-size inverter drives metal 1 wire of 2000 x 3. –R 0 = 3.9 k , C 0 = 0.68 fF, R int = 53.3 k , C int = fF. n Then –k = –H = –T 50% = 9.64 E-12

Modern VLSI Design 4e: Chapter 3 Copyright  2008 Wayne Wolf RC crosstalk n Crosstalk slows down signals---increases settling noise. n Two nets in analysis: –aggressor net causes interference; –victim net is interfered with.

Modern VLSI Design 4e: Chapter 3 Copyright  2008 Wayne Wolf Aggressors and victims victim net aggressor net

Modern VLSI Design 4e: Chapter 3 Copyright  2008 Wayne Wolf Wire cross-section n Victim net is surrounded by two aggressors. victimaggressor substrate W S T H

Modern VLSI Design 4e: Chapter 3 Copyright  2008 Wayne Wolf Crosstalk delay vs. wire aspect ratio Increasing aspect ratio relative RC delay increased spacing

Modern VLSI Design 4e: Chapter 3 Copyright  2008 Wayne Wolf Crosstalk delay n There is an optimum wire width for any given wire spacing---at bottom of U curve. n Optimium width increases as spacing between wires increases.

Modern VLSI Design 4e: Chapter 3 Copyright  2008 Wayne Wolf RLC transmission lines n Most results come from curve fitting. Propagation delay is largely a factor of  50% propagation delay can be calculated in terms of 

Modern VLSI Design 4e: Chapter 3 Copyright  2008 Wayne Wolf Kahng/Muddu model n Analytical model of similar complexity to Elmore model. n Let R s, L s be source impedance, R int, C int, L int be transmission line impedance, C L be load impedance. n Delay t = K C 2b 2 /sqrt(4b 2 – b 1 2 ), K C usually 1.66.

Modern VLSI Design 4e: Chapter 3 Copyright  2008 Wayne Wolf Switch logic n Can implement Boolean formulas as networks of switches. n Can build switches from MOS transistors— transmission gates. n Transmission gates do not amplify but have smaller layouts.

Modern VLSI Design 4e: Chapter 3 Copyright  2008 Wayne Wolf Types of switches

Modern VLSI Design 4e: Chapter 3 Copyright  2008 Wayne Wolf Behavior of n-type switch n-type switch has source-drain voltage drop when conducting: –conducts logic 0 perfectly; –introduces threshold drop into logic 1. V DD V DD - V t

Modern VLSI Design 4e: Chapter 3 Copyright  2008 Wayne Wolf n-type switch driving static logic Switch underdrives static gate, but gate restores logic levels. V DD V DD - V t

Modern VLSI Design 4e: Chapter 3 Copyright  2008 Wayne Wolf n-type switch driving switch logic Voltage drop causes next stage to be turned on weakly. V DD V DD - V t V DD

Modern VLSI Design 4e: Chapter 3 Copyright  2008 Wayne Wolf Behavior of complementary switch n Complementary switch products full-supply voltages for both logic 0 and logic 1: –n-type transistor conducts logic 0; –p-type transistor conducts logic 1.

Modern VLSI Design 4e: Chapter 3 Copyright  2008 Wayne Wolf Layout characteristics n Has two source/drain areas compared to one for inverter. n Doesn’t have gate capacitance.